A theoretical and experimental analysis of the buried-source VMOS dynamic RAM cell

The buried-source dynamic RAM cell combines a VMOS transistor (VMOST) and a buried junction capacitor to make a one-transistor cell (1TC) providing large storage capacitance, long charge retention, and high density. The threshold voltage, breakdown voltage, and weak inversion current for the forward and reverse modes of operation of the VMOST and the junction capacitance are experimentally related to the nonuniform doping profile of the channel. Equations are developed for the VMOST short-channel threshold voltage and storage capacity of the cell. The charge capacity (per unit of cell area) of the buried-source cell is calculated to be 2.5 times that of the conventional 1TC cell. The cell charge retention time was measured at more than 1 s at 100°C, proving operation of the device as a dynamic memory element. The technology is capable of producing an 80-µm²cell using 4-µm minimum features, no cell contacts, and a single level of interconnect.     

An experimental study of the BO-MOS dynamic RAM cell

A novel structure of a one-transistor dynamic MOS RAM cell is developed for higher integration. The buried-oxide MOS (BO-MOS) RAM cell consists of a planar MOSFET transfer gate and a storage capacitor of buried N⁺diffusion. This three-dimensional structure results in a cell size of6F^{2}with a minimum feature sizeFand the large capacitance ratio of storage to bit-line which is about 4 times that of a typical commercial 64-kbit RAM cell. The soft-error-immunity cell structure is also taken into account. Static device characteristics of the planar MOSFET transfer gate built on an epitaxial layer and the buried storage capacitance are investigated relating to doses of boron implantation to the channel and substrate. Dynamic WRITE/READ operations are performed with an experimental 4 × 10 cell array implemented withF = 4-µm features. The technology offers the possibilities of a high density dynamic MOS RAM with a single poly-Si process.     

A new cell structure with a spread source/drain (SSD) MOSFET and acylindrical capacitor for 64-Mb DRAM's

A new cell structure for realizing a small memory cell size has been developed for 64-Mb dynamic RAMs (DRAMs). The source/drain regions of a switching transistor are raised by using a selective silicon growth technique. Because of lateral growth of the silicon over gate and field regions, the bitline contact can overlap the gate and field regions. The shallow source/drain junction by the raised source/drain structure realizes a reduction of gate length and isolation spacing. As a result, the DRAM memory cell area can be reduced to 37% of that using the conventional LDD MOSFET. In the fabrication of an experimental DRAM cell, a new stacked capacitor structure has been introduced to maintain enough storage capacitance, even in the small-cell area. The new capacitor is made by a simple and unique process using a cylindrical silicon-nitride sidewall layer. It has been verified that this cell structure has the potential to realize multimegabit DRAMs, such as 64-Mb DRAMs     

Operating principles and performance of a novel a-Si:H p-i-n-based X-ray detector for medical image applications

This work develops a novel hydrogenated amorphous silicon (a-Si:H) p-i-n photodiode-based X-ray detector aimed at medical image applications. The new detector consists of an a-Si:H p-i-n photodiode and a stacked dielectric layer, deposited on the p-layer (n-i-p-SiN/sub x/) or the n-layer (p-i-n-SiN/sub x/) of the p-i-n photodiode, as the main charge storage element. This detector operates as a capacitor and is connected in parallel to a reverse-biased p-i-n photodiode during the detection cycle to accumulate photon-converted charges. The junction capacitance (C/sub j/) of the p-i-n diode was enhanced by this stacked dielectric layer without reducing the active area of the detector. The design of the charge storage capacity and the photon-charge transfer efficiency can be optimized separately for various applications. Moreover, the linearity, dynamic range of operation, and data retention capacity of the detector were found to be markedly improved by the enlarged capacitance in the detector. The operating principles and performance of this novel device are discussed, and the corresponding control sequence of the switch of the device array is also addressed. The experimental results proved that this novel structure is valid and can be applied to construct effectively a two-dimensional detection array, offering considerable advantages of the novel device in X-ray medical image applications.     

The COB stack DRAM cell at technology node below 100 nm-scalingissues and directions

The scaling of the 8F² COB stack DRAM cell down to 70-nm technology node is described. Issues and possible solutions regarding critical points, such as the difficulty in achieving sufficient memory cell capacitance, degraded cell transistor performance, and increased junction leakage current at storage node are investigated. Although its unit cell size is bigger than those of open bit line cell architectures, the 8F² COB stack cell can be the most suitable technology for 70-mn DRAM technology node due to its excellent noise immunity and large capacitor area     

Forward-voltage capacitance and thickness of p-n junction space-charge regions

A comprehensive analytical model for the quasi-static capacitance of the space-charge region of p-n junction devices is presented. It describes the capacitance for all voltages, including voltages large enough to cause the junction barrier to vanish. The model applies for exponential-constant doping profiles, the limiting cases of which are the step and the linear-graded profiles. In addition to the analytical model, an iterative technique is developed to yield numerically the thickness of the space-charge region as a function of voltage. The capacitance model shows good agreement when compared with measured dependencies, With an empirical model for circuit simulation, and with models based on device simulation. The model extends previous replacements of the depletion capacitance, provides a tool for circuit simulation, and is intended to provide understanding of the physics related to storage of mobile holes and electrons in the junction space-charge region.     

The behavior of the continuously charge-coupled random-access memory (C/SUP 3/RAM)

This paper describes a new random-access memory which achieves a bit density comparable to CCD memories. This memory uses as storage elements single-transistor memory cells which are connected to a common bit line. The bit line is implemented with an MOS transmission line, which makes possible an almost lossless charge transport from the single-transistor memory cell to the read/write amplifier. Due to the almost lossless charge transport, the storage capacitance can be reduced and the bit density increased. The expected performance of a 32-kbit memory has been derived.     

Capacitance and conductance of ZnxCd1-xS/ZnTeheterojunctions

Capacitance-voltage and conductance-voltage characteristics of RF-sputtered ZnCdS films on ZnTe single crystals are studied as a function of frequency up to 1 MHz. It is found that the measured capacitance decreases with frequency while the conductance increases. A physical circuit model of the junction is proposed to explain this dependence. A relationship relating the junction capacitance to the polycrystalline film properties and the built-in voltage of the junction is derived. It shows that the junction capacitance is related to the average carrier concentration rather than the doping concentration of the polycrystalline material. From a C^-2 versus V plot an average carrier concentration in the films which is in good agreement with that obtained by Hall measurement is obtained. The lower average electron concentration in the ZnCdS film near the substrate is due to either interdiffusion of Cd from the film into substrate or due to higher density of grain boundary states in the starting deposition portion of the film     

A 34 /spl mu/m/SUP 2/ DRAM cell fabricated with a 1 /spl mu/m single-level polycide FET technology

Dynamic RAM test arrays have been fabricated using a single-level polycide FET technology and a cell layout in which the top electrode of a given cell storage capacitor is provided by the adjacent word line. This layout achieves the same density as the conventional double-polysilicon cell, and comparable performance is obtained using a low-resistance polycide word line. Hi-C implants in the storage region provide increased capacitance, better isolation, and reduced transient noise. Design and operation considerations for the cell and arrays are described and measured results are compared to the design values. A cell area of 34 /spl mu/m/SUP 2/ is achieved using a scaled-down n-channel FET technology with a 22.5 nm gate oxide and 1 /spl mu/m minimum mask feature size.     

Junction capacitance reduction due to self-aligned pocketimplantation in elevated source/drain NMOSFETs

A new advantage of an elevated source/drain (S/D) configuration to improve MOSFET characteristics is presented. By adopting pocket implantation into an elevated S/D structure which was formed by Si selective epitaxial growth and gate sidewall removal, we demonstrate that the parasitic junction capacitance as well as the junction leakage was significantly reduced for an NMOSFET while maintaining its good short channel characteristics. These successful results are attributed to the modification of the boron impurity profile in the deep S/D regions. The capacitance reduction rate, furthermore, was more remarkable as the pocket dose was further increased. This means that the present self-aligned pocket implantation is very promising for future MOSFETs with a very short gate length, where high pocket dosage will be required to suppress the short channel effect     

Submicrometer-channel CMOS for low-temperature operation

A 0.5-µm-channel CMOS design optimized for liquid-nitrogen temperature operation is described. Thin gate oxide (12.5 nm) and dual polysilicon work functions (n⁺-poly gate for n-channel and p⁺-poly for p-channel transistors) are used. The power supply voltage is chosen to be 2.5 V based on performance, hot-carrier effects, and power dissipation considerations. The doping profiles of the channel and the background (substrate or well) are chosen to optimize the mobility, substrate sensitivity, and junction capacitance with minimum process complexity. The reduced supply voltage enables the use of silicided shallow arsenic and boron junctions, without any intentional junction grading, to control short-channel effects and to reduce the parasitic series resistance at 77 K. The same self-aligned silicide over the polysilicon gate electrode reduces the sheet resistance (as low as 1 Ω/sq at 77 K) and provides the strapping between the gates of the complementary transistors. The design has been demonstrated by a simple n-well/p-substrate CMOS process with very good device characteristics and ring-oscillator performance at 77 K.     

Effects of the Diode Junction Capacitance on the Conversion Loss of Microwave Mixers

The theory of the frequency down-converters, which use sinusoidally driven exponential junction diode, is reviewed here with the purpose of investigating the effects of the junction Capacitance on the conversion loss. The analysis deals With single-ended mixers, both in theZandYconfigurations. Their performances are compared with those obtained from the same configurations of mixers using a purely resistive (PR) exponential diode, in cases of both short-circuited and open-circuited image frequency. This comparison shows that the junction capacitance modifies strongly the behavior of the single-ended mixer compared tothe case of purely resistive diodes. It is pointed out that, when the junction capacitance may not be neglected, and the image frequency is either open- or short-circuited, good performance can still be achieved from a sinusoidally drivenYmixer. On the contrary, the sinusoidally drivenZmixer, which Operates better than theYmixer when the effect of the junction capacitance may be neglected, is strongly deteriorated, and it becomes worse than theYmixer.     

A Dynamic Optically Reconfigurable Gate Array—Perfect Emulation

This paper presents a perfect dynamic optically reconfigurable gate array (DORGA) architecture emulation using a holographic memory and a conventional ORGA-VLSI. In ORGAs, although a large virtual gate count can be realized by exploiting the large-capacity storage capability of a holographic memory, the actual gate count, which is the gate count of a programmable gate array VLSI, is important to increase the instantaneous performance. Nevertheless, in previously proposed ORGA-VLSIs, the static configuration memory to store a single configuration context consumed a large implementation area of the ORGA-VLSIs and prevented the realization of large-gate-count ORGA-VLSIs. Therefore, a DORGA architecture has been proposed in order to increase the gate density. It uses the junction capacitance of photodiodes as dynamic memory, thereby obviating the static configuration memory. However, to date, demonstration of a perfect optically reconfigurable architecture for DORGA-VLSIs has never been presented. Therefore, in this study, the DORGA architecture was perfectly emulated, and the performance, particularly the reconfiguration context retention time, was measured experimentally. The advantages of this architecture are discussed in relation to the results.     

A novel SOI-DTMOS structure from circuit performance considerations

The performance of a partially depleted silicon-on-insulator (PDSOI) dynamic threshold MOSFET (DT-MOS) is degraded by the large body capacitance and body resistance. Increasing silicon film thickness can reduce the body resistance greatly, but the body capacitance also increases significantly at the same time. To solve this problem, a novel SOI DTMOSFET structure (drain/source-on-local-insulator structure) is proposed. From ISE simulation, the improvement in delay, obtained by optimizing p-n junction depth and silicon film thickness, is very significant. At the same time, we find that the drive current increases significantly as the thickness of the silicon film increases. Furthermore, only one additional mask is needed to form the local SIMOX, and other fabrication processes are fully compatible with conventional CMOS/SOI technology.     

A capacitance-coupling memory cell operating with a single powersupply

A capacitance-coupling (CC) memory cell structure is proposed that operates with a single power supply and provides larger storage capacitance than the conventional CC cell. This structure uses triple polysilicon technology and a self-aligned positioning technique. To obtain single-power-supply operation, two word lines are used for reading and writing. The p-channel MOSFET and the junction FET, which are included in the memory cell and are merged in one device area, are extensively studied to estimate the capability of the cell. Experimental memory cells with 1-μm design rule were fabricated that showed complete memory operation and sufficient 0/1 readout-current ratio, and also confirmed the estimated capability results     

从电路特性方面考虑而提出的SOI-DTMOS新结构

The performance of a partially depleted silicon-on-insulator （PDSO1） dynamic threshold MOSFET （DT- MOS） is degraded by the large body capacitance and body resistance. Increasing silicon film thickness can reduce the body resistance greatly, but the body capacitance also increases significantly at the same time. To solve this problem, a novel SOl DTMOSFET structure （drain/source-on-local-insulator structure） is proposed. From ISE simulation, the improvement in delay, obtained by optimizing p-n junction depth and silicon film thickness, is very significant. At the same time, we find that the drive current increases significantly as the thickness of the silicon film increases. Furthermore, only one additional mask is needed to form the local SIMOX, and other fabrication processes are fully compatible with conventional CMOS/SOI technology.     

STI stress-induced increase in reverse bias junction capacitance

A new contribution to reverse-biased junction capacitance is reported. This component arises from trench isolation stress-induced bandgap narrowing that changes the built-in potential. Experimental junction capacitance measurements show good correlation to simulated oxidation stresses. The reported data agrees well with the predicted values from basic device equations. Stress induced capacitance increase of 12% (7.5%) at 3.3 V reverse bias for p⁺/n (n⁺/ p) junctions, respectively is observed. In addition, well-understood reverse junction leakage relation to stress is also reported. This phenomenon will become increasingly important as trenches become shallower and more tightly spaced     

A random noise reduction method for an amorphous siliconphotoconversion layer overlaid CCD imager

A novel random noise reduction (RNR) method, which can reduce random noise generated in a storage diode (SD), has been proposed and evaluated with a cell test element. The RNR cell structure features an RNR transistor with a second storage diode, which is inserted between the SD and a vertical CCD (V-CCD). The RNR transistor controls the transfer channel potential and suppresses the random noise generated in the SD. Net first storage diode capacitance with the RNR transistor can be reduced down to (C_f×C_a)/(C_f+m×C_a ), where C_f is the second storage diode capacitance, C _a is the first storage diode capacitance, and m is the channel potential modulation factor. Experimentally, the RNR cell can reduce the random noise in the SD from 42 electrons [r.m.s.] down to 18 electrons [r.m.s.] for the SD capacitance of 5 fF. This makes it possible for the photoconversion layer overlaid CCD imager with the RNR cells to reproduce video images with a high S/N ratio     

A dynamic RAM Cell in recrystallized polysilicon

A new, one-transistor, dynamic RAM cell has been fabricated in beam-recrystallized polysilicon. Placing thin oxides both above and below the storage region doubles the storage capacitance. Complete isolation of the storage region by oxides also reduces the susceptibility of the cell to soft errors from collection of charge injected into the substrate by the surrounding elements or by alpha particles. Long storage times are feasible, being limited only by the leakage of the access transistor. A thick oxide under the bit line reduces the bit-line capacitance, further increasing the ratio of storage capacitance to bit-line capacitance.     

A Novel 4.5$hbox{F}^{2}$ Capacitorless Semiconductor Memory Device

This letter proposes a novel 4.5$hbox{F}^{2}$ capacitorless dynamic random access memory cell with a floating gate (FG) connected to drain via a gated p-n junction diode. The FG in the proposed memory device is for charge storage and can electrically be charged or discharged by current flowing through a gated p-n junction diode.