Monolithic analog adaptive equalizer integrated circuit for wide-band digital communication networks

This equaliser is presented with particular emphasis on architecture and performance. To reduce the size, cost, and power dissipation, and to improve the operation speed and performance, this equalizer IC employs many techniques such as all analog signal processing with parallel updating the weights and eliminating the offset according to the least mean-square algorithm, MOS VLSI fabrication process and switched capacitor technique. As the key building blocks, low- and high-speed MOS operational amplifiers and four-quadrant analog multipliers are specially developed. The 16 mm/SUP 2/ chip providing 5 taps operates on /spl plusmn/5 and 10 V power supplies with power dissipation of 570 mW. The maximum data rate is more than 200 kHz. For the linear adaptive equalizer configuration operating at a data rate of 100 kHz, the residual RMS distortion and convergence time are measured to be -40 dB and about 2 ms (200 iterations), respectively, when a binary signal with an initial RMS distortion of 40 percent (-7.96 dB) is applied.     

A dual differential charge-coupled analog delay device

A dual differential charge-coupled analog device providing signal delays of 24 and 48 elements has been designed for sampled data analog signal processing applications. The aim of this design was to eliminate some of the disadvantages that have been associated with previous charge-coupled devices (CCD's). These include clock pickup, thermally generated dc offsets, and complex external control and amplification circuitry. The device has an input strobing circuit and an on-chip output amplifier. With a clock frequency of 8 kHz and a 400-mV rms input signal, the total harmonic distortion was below 0.2 percent and the signal-to-noise ratio was better than 70 dB with a 4-kHz bandwidth. The device gain was 6 dB and a gain variation of 0.2 dB was observed over a temperature range of 0 to 55°C.     

Double-split-electrode transversal filter for telecommunication applications

A novel structure for on chip tap weight implementation in CCD transversal filters is described which employs two splits in the CCD sensing electrodes to improve on the performance of the conventional single-split weighting technique. This greatly reduces the capacitance associated with the sensing nodes and consequently reduces the common mode signal, gain sensitivity, coefficient error, and clock noise pickup. Experimental results are presented which verify this improved performance. The results achieved for a 3.4-kHz low-pass filter clocked at 32 kHz show a signal-to-noise ratio of 86 dB with harmonic distortion of less than 0.3 percent.     

A 300-MHz fixed-delay tree search-DFE analog CMOS disk-drive readchannel

A decision feedback equalizer (DFE) with digital error detection and correction implements a fixed-delay tree search with depth of 2. The disk-drive read waveform is first equalized to EPR4 for clock recovery and then re-equalized to the DFE target. A mostly analog implementation of this read channel in 0.6-μm CMOS implements a tapped delay-line forward filter with a cascade of track-and-hold circuits and variable transconductors. Using MTR (2,k) code, the compact read channel IC surpasses a conventional EPR4 read channel with Viterbi detector at user densities in the range 2.0-3.0     

A dual differential charge-coupled analog delay device

A dual differential charge-coupled analog device providing signal delays of 24 and 48 elements has been designed for sampled data analog signal processing applications. The aim of this design was to eliminate some of the disadvantages that have been associated with previous charge-coupled devices (CCD's). These include clock pickup, thermally generated d.c. offsets, and complex external control and amplification circuitry. The device has an input strobing circuit and an on-chip output amplifier. With a clock frequency of 8 kHz and a 400-mV r.m.s. input signal, the total harmonic distortion was below 0.2 percent and the signal-to-noise ratio was better than 70 dB with a 4-kHz bandwidth. The device gain was 6 dB and a gain variation of 0.2 dB was observed over a temperature range of 0 to 55/spl deg/C.     

Design Considerations for a 144 kbit/s Digital Transmission Unit for the Local Telephone Network

In this paper a digital transmission unit for the forthcoming integrated services digital network (ISDN) is considered. Basic elements of such a unit are an adaptive echo canceller (EC) and an adaptive decision feedback equalizer (DFE). Each of these filters can be realized by a transversal filter structure or by a lookup table structure. An analysis and comparison of the behavior of these two structures is given, The combination of an EC and a DFE can also be realized by a single lookup table. It is shown that irrespective of the particular realization three different convergence phases can be distinguished, and that the overall convergence time is considerably longer then would be expected from the usual simple theory that ignores error propagation in the DFE. Two variants of a hardware realization of such a digital transmission unit are presented. They provide 144 kbit/s full-duplex transmission on the symmetrical cables of the existing local telephone network. A small transmission bandwidth is obtained by applying NRZ signaling. In the first circuit the EC and DFE are implemented by individual lookup tables, while in the second a combined table is used. Both circuits are to a large extent, implemented digitally. Due to the relatively low sampling frequency and the acceptably low power consumption they are very well suited for large scale integration with present day technology.     

自适应均衡算法在信道均衡技术中的应用研究

文中描述了两种非线性均衡器分别为判决反馈均衡器(DFE)和最大似然序列估计(MLSE)均衡器.所用信道模型为加性白高斯噪声信道,在DFE和线性均衡器(LE)中都是使用递归最小二乘(RLS)算法和最小均方(LMS)算法对数据进行分块处理.MLSE均衡器中使用了维特比最佳译码算法.就误比特性能来做以比较,DFE远好于LE,MLSE均衡器又明显优于DFE,并且它能达到几乎最优的性能.     

一个用于背板通信的24Gb/s高速自适应组合均衡器

本文介绍了应用于背板通信系统中均衡器的设计与实现.该均衡器采用连续时间线性均衡器（Continuous Time Linear Equalizer,CTLE）和2抽头判决反馈均衡器（Decision Feedback Equalizer,DFE）的组合结构来消除信道码间干扰中的前标分量和后标分量.在设计中,CTLE采用双路均衡器结构补偿信道不同频率的损耗,减小了电路的面积和功耗;DFE采用半速率预处理结构来缓解传统DFE结构中关键反馈路径的时序限制,并采用模拟最小均方（Least Mean Square,LMS）算法电路控制DFE系数的自适应.电路采用IBM 0.13μm BiCMOS工艺设计并实现,测试结果表明对于经过18英寸背板后眼图完全闭合的24Gb/s的信号,均衡后的眼图水平张开度达到了0.81UI.整个均衡器芯片包括焊盘在内的芯片面积为0.78×0.8mm²,在3.3V的电源电压下,功耗为624mW.     

Tentative chip decision-feedback equalizer for multicode wideband CDMA

We investigate a chip-level minimum mean-square-error (MMSE) decision-feedback equalizer (DFE) for the downlink receiver of multicode wideband code-division multiple-access systems over frequency-selective channels. First, the MMSE per symbol achievable by an optimal DFE is derived, assuming that all interchip interference (ICI) of the desired user can be eliminated. The MMSE of DFE is always less than or at most equal to that of linear equalizers (LE). When all the active codes belong to the desired user, the ideal DFE is able to eliminate multicode interference (MCI) and approach the performance of the single-code case at high signal-to-noise ratio (SNR) range. Second, we apply the hypothesis-feedback equalizer or tentative-chip (TC)-DFE in the multicode scenario. TC-DFE outperforms the chip-level LE, and the DFE that only feeds back the symbols already decided. The performance gain increases with SNR, but decreases with the number of active codes owned by the other users. When all the active codes are assigned to the desired user, TC-DFE asymptotically eliminates MCI and achieves single-user (or code) performance at high SNR, similarly, to the ideal DFE. The asymptotic performance of the DFE is confirmed through bit error rate simulation over various channels.     

A BIST Solution for Frequency Domain Characterization of Analog Circuits

This work presents an efficient implementation of a BIST solution for frequency characterization of analog systems. It allows a complete characterization in terms of magnitude and phase, including also harmonic distortion and offset measurements. Signal generation is performed using a modified filter, while response evaluation is based on 1st-order ΣΔ modulation and very simple digital processing. The signal generator and the response analyzer have been implemented using the Switched-Capacitor (SC) technique in a standard 0.35 μm–3.3 V CMOS technology. Both circuits have been separately validated, and an on-board prototype of the complete test system for frequency characterization has been implemented. Experimental results verify the functionality of the proposed approach, and a dynamic range of 70 dB@62.5 kHz (1 MHz clock) has been demonstrated.     

A mixed-signal RAM decision-feedback equalizer for disk drives

A mixed-signal RAM decision-feedback equalizer (DFE) that operates at 90 Mb/s is described. In the analog domain, the DFE subtracts intersymbol interference caused by the past four outputs. The equalized signal is fed into a nonuniform flash analog-to-digital converter (ADC) to produce the decision output and error signal used to adapt the RAM contents in the digital domain. With a 5 V supply voltage, the power dissipation is 260 mW during steady-state operation. The active area is 4.5 mm² in a 1 μm CMOS process     

应用于10 Gbit/s光通信及背板传输的自适应均衡器设计

描述了一种既可用于背板传输也可用于光纤通信的高速串行收发器前端均衡器的设计。为适应光信号在传播中的色散效应,使用前馈均衡器(FFE)加判决反馈均衡器(DFE)的组合,取代了背板通信中常用的连续时间线性均衡器(CTLE)和DFE的组合。设计使用3 pre-tap、3 post-tap和1个main tap的抽头组合方式,兼顾pre-cursor和post-cursor的信号失真,有效补偿范围为15 dB。补偿系数采用完全自适应算法调整,对FFE采用模拟MSE算法调整,DFE引擎采用1/16速率数字sign-sign最小均方差(LMS)算法实现。芯片使用UMC 28 nm工艺流片,输入信号频率为10 Gbit/s。     

运用误差反馈的判决反馈均衡器的性能分析

判决反馈均衡器（Decision Feedback Equalizer，DFE）能补偿具有严重符号间干扰（Inter Symbol Interference，ISI）的信道，且不存在线性均衡器增强噪声的影响。而在其基础上改进的运用误差反馈的DFE，可利用误差反馈滤波器来减少传统DFE中存在的误差信号的相关性，同时其硬件实现的复杂度没有明显提高。理论分析和仿真表明，这种方法比传统的DFE更有效，特别是针对信道有严重符号间干扰的情况。     

Fully balanced CMOS current-mode circuits

A fully balanced current-mode circuit topology has been developed for analog signal processing applications. The basic building block, a 5-V fully balanced current mirror/amplifier, has been fabricated using a standard 2-μm n-well CMOS process. With a peak signal to bias current ratio i/I=0.5, the open-loop total harmonic distortion was-70 dB. With the addition of sampling switches, the current mirror/amplifier forms a fully balanced switched-current integrator that exhibits first-order cancellation of clock-feedthrough/charge-injection effects. Fully balanced SI ladder filters have been implemented using a 2-μm p-well CMOS process. For a sampling frequency of 128 kHz, the five-pole Chebyshev low-pass ladder filters met design specifications of 0.1-dB passband ripple and 5-kHz bandwidth. The dynamic range was 81.5 dB, and the total power dissipation was 14 mW with V_dd 5 V     

A 1.6-GS/s 12-bit return-to-zero GaAs RF DAC for multiple Nyquist operation

A 12-bit 1.6-GS/s digital-to-analog converter (DAC) implemented with 4-/spl mu/m/sup 2/ GaAs HBT process is presented. Return-to-zero (RZ) current switches are added to current steering DAC for high-frequency wideband applications to achieve 800-MHz bandwidth at first and second Nyquist band without the need for a reverse sinc equalization filter in wideband transmitter application. The RZ circuit also improves spectral purity by screening the switching noise from the analog output during data transition. Measured performance shows two-tone third-order harmonic distortion of -70 dB at 1.5-GHz output frequency, clocked at 1.6 GHz. Reliable interface with CMOS logic IC is guaranteed with the inclusion of a four-clock-deep FIFO circuit. The DAC dissipates 1.2 W at -5 V when sampled with 1.6-GHz clock, with typical output voltage swing of 1.2 V/sub PP/.     

滑动窗快速横向滤波的自适应判决反馈均衡器算法

本文提出了一种基于滑动窗广义多路快速横向滤波（ＳＷＦＴＦ）的自适应判决反馈均衡器（ＤＦＦ）算法，它具有快速跟踪性能，故可用于快速时变多径衰落的信道。文中推导了ＳＷＦＴＦ－ＤＦＥ算法。在数字移动通信信道模型上，利用计算机模拟，在均方误差和误码率特性方面与其它均衡器算法进行了比较。     

An ISDN echo-cancelling transceiver chip set for 2B1Q coded U-interface

A three-chip set for a 2B1Q U-interface transceiver has been developed. The chip set is composed of an analog front-end (AFE), echo-canceller (EC), and receiver (RCV) LSIs. The AFE LSI includes a 12-b accuracy oversampling analog/digital converter. The EC and RCV LSIs are 26- and 16-bit microprogrammable digital signal processors, respectively. A digital phase-locked loop is used to minimize the analog part. Residual echo increase by a timing phase jump is compensated for by a newly introduced additional adaptive filter. Infinite impulse response filters and multiresponse filters reduce the necessary number of taps for both the echo canceller and the decision-feedback equalizer. The AFE and the two digital signal processor LSIs are implemented in 1.6- and 1.2-μm double-metal layer CMOS processes, respectively. A 6-km loop coverage was realized with a less than 10^-7 error rate. Total power consumption by the chip set is 580 mW at 5-V single supply     

A Reduced Complexity Equalizer for OQPSK

This letter presents a reduced complexity equalizer for offset quadrature phase-shift keying (OQPSK), Gaussian minimum shift keying (GMSK), or any other staggered modulation format. Due to the relative time offset of the in-phase and quadrature components, the received signal must be sampled at a rate of at least twice the symbol rate of its corresponding nonstaggered signal, where using a symbol-spaced equalizer (SSE) is an option. The conventional approach doubles the number of equalizer coefficients required relative to QPSK. In this work it is shown that also for OQPSK it is possible to implement an equalizer spaced in symbol rate, with about half the complexity required for the linear equalizer (LE). For the decision feedback equalizer (DFE), savings are achieved only in the feed forward filter.     

Adaptive decision feedback equalization for digital satellitechannels using multilayer neural networks

This paper introduces an adaptive derision feedback equalization using the multilayer perceptron structure of an M-ary PSK signal through a TDMA satellite radio channel. The transmission is disturbed not only by intersymbol interference (ISI) and additive white Gaussian noise, but also by the nonlinearity of transmitter amplifiers. The conventional decision feedback equalizer (DFE) is not well-suited to detect the transmitted sequence, whereas the neural-based DFE is able to take into account the nonlinearities and therefore to detect the signal much better. Nevertheless, the applications of the traditional multilayer neural networks have been limited to real-valued signals. To overcome this difficulty, a neural-based DFE is proposed to deal with the complex PSK signal over the complex-valued nonlinear MPSK satellite channel without performing time-consuming complex-valued back-propagation training algorithms, while maintaining almost the same computational complexity as the original real-valued training algorithm. Moreover, a modified back-propagation algorithm with better convergence properties is derived on the basis of delta-bar-delta rule. Simulation results for the equalization of QPSK satellite channels show that the neural-based DFE provides a superior bit error rate performance relative to the conventional mean square DFE, especially in poor signal-to-noise ratio conditions     

A volume and tone control IC for Hi-Fi audio

A monolithic IC which contains dual-channel volume control circuits, tone control circuits, and function switches is discussed. The IC has excellent characteristics, such as total harmonic distortion of less than 0.002 percent (at 1 kHz, 300 mV rms input signal) and a signal-to-noise ratio of more than 100 dB (at 300 mV rms input signal, A weighting). SIPOS-gate MOSFET's and polysilicon ion implanted resistors are employed, yielding good signal level accuracy and low distortion.