一种基于RRAM和表决器逻辑的新型乘法器

计算机系统快速发展,逐步进入大内存系统时代。但存储瓶颈的问题严重制约着计算机系统的进一步发展。结合RRAM这种非易失性存储器,设计了一种可以实现存储与计算一体化的逻辑运算架构。首次利用多数表决器逻辑实现了一种新型的全加器和乘法器,并给出了一种新型的逻辑运算单元架构。试验结果表明,该多数表决器逻辑实现全加器仅需4个步骤、3个单元,实现乘法器仅需24个步骤、42个单元,远远低于目前其他逻辑所需的步骤数和单元数。

A New Multiplier Based on RRAM and Majority-Inverter-Graph Logic

With the rapid development, the computer systems are entering the era of large memory systems. However, the memory bottleneck problems seriously constrain the further development of computer systems. A novel logical computing architecture for storage and computation combined with RRAM(i.e. a non-volatile memory) was proposed. A new type of full adder logic and multiplier using the majority-inverter-graph logic was designed first, and a new ALU architecture was given. Experimental results showed that a full adder was implemented by the majority-inverter-graph logic with only 4 steps and 3 memristors, and a multiplier was implemented with only 24 steps and 42 memristors. The required numbers of steps and memristors were much less than that of other logic.