基于FPGA的事件抽取模型与加速器的设计实现

Design and implementation of event extractionmodel and accelerator based on FPGA

Event extraction technology is important to achieve the quickly extraction of specific information, and it can be widely used in information retrieval, sentiment analysis and other scenarios. Chinese event extraction is more difficult than English event extraction due to the characteristics of Chinese language. Based on the state of the art English event extraction neural network model, a CEE DGCNN (Chinese Event Extraction based on multi layer Dilate Gated Convolutional Neural Network) is proposed, which is suitable for hardware implementation. CEE DGCNN achieves 71.71% F1 score of trigger classification on the ACE2005 Chinese corpus. The accelerator of CEE DGCNN is designed and implemented, and the model size is further optimized by quantization. The accelerator can achieve 97 GOP/s on the Xilinx XCKU115 FPGA, which is 67 times faster than CPU.