| CMOS图像传感器中数字噪声抑制技术研究 |
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| 引用本文： | 刘洪文,张生才,姚素英,徐江涛. CMOS图像传感器中数字噪声抑制技术研究[J]. 光电子．激光, 2007, 18(4): 411-413 |
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| 作者姓名： | 刘洪文 张生才 姚素英 徐江涛 |
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| 作者单位： | 天津大学电子信息工程学院,ASIC设计中心,天津,300072 |
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| 基金项目： | 国家自然科学基金 , 天津市科技攻关项目 |
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| 摘 要： | 设计了一种可以降低CMOS图像传感器(CIS)中数字噪声对模拟信号影响的时序.在时序控制电路中加入了门控时钟,使数字电路各模块可分时工作,在模拟电路采样阶段保持静止以抑制噪声.理论分析和测试结果表明,采样阶段噪声减小70%,其他时间噪声减小20%.
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| 关 键 词： | CMOS图像传感器(CIS) 数字噪声 时序 静止期采样 |
| 文章编号： | 1005-0086（2007）04-0411-03 |
| 修稿时间： | 2006-06-04 |
Research of Digital Noise Reduction Technique in CMOS Image Sensor |
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| LIU Hong-wen,ZHANG Sheng-cai,YAO Su-ying,XU Jiang-tao. Research of Digital Noise Reduction Technique in CMOS Image Sensor[J]. Journal of Optoelectronics·laser, 2007, 18(4): 411-413 |
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| Authors: | LIU Hong-wen ZHANG Sheng-cai YAO Su-ying XU Jiang-tao |
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| Abstract: | A timing circuit is designed to reduce the effect of digital noise on analog signal in CMOS image sensor(CIS).Each module of the digital circuits can work time-sharing by adding gated-clocks ware and it can keep quiet to suppress onise when analog circuits are sampling.Theory analysis and experimental results show that the noise at sampling is reduced by 70%,and 20% in other time.The method to keep digital circuit quiet when analog circuits are sampling can be extended to all high-precision mixed-signal integrated circuits design. |
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| Keywords: | CMOS image sensor(CIS) digital noise timing quiet period sampling |
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