一种高增益低功耗CMOS LNA设计

采用TSMC0.18μmCMOS工艺,利用ADS2008软件仿真,设计了一种高增益的CMOS低噪声放大器。与传统的共源共栅结构相比,该电路在晶体管M3的栅源极处并入电容C1,以增加系统抗干扰能力;并在级间引入一并联电感和电容与寄生电容谐振,以提高增益。仿真结果表明,在2.4 GHz工作频率下,该电路的增益大于20 dB,噪声系数小于1 dB,工作电压为1.5 V,功耗小于5 mW,且输入输出阻抗匹配良好。

Design on High-gain and Low-power CMOS Low-noise Amplifier

A low-power CMOS LNA with ADS2008 based on TMSC’s 0.18μm CMOS technology is designed and simulated.Compared with traditional cascade structure,this circuit,with a capacitor C1 inserted between gate and source of transistor,could improve anti-interference ability of the system,while with an inductor and capacitor resonance in inter-stage parasitic capacitor,could improve the system gain.Simulation results indicate that,operating at 2.4GHz,the circuit could achieve a gain of above 20 dB and a noise figure of below 1dB,the power dissipation is below 5mW from 1.5V supply,and the input output impedances match well.