SPAD阵列读出电路关键技术与发展趋势(特邀)

首先针对SPAD阵列读出电路的特点，将电路主要分成接口电路与信号处理电路两大部分，其次根据单光子雪崩光电探测器的阵列的不同应用场景，阐述了集成读出电路中核心电路模块设计的关键技术。分别从SPAD的接口电路设计、两种典型应用成像模式(光子计时、光子计数)中核心电路的设计方面，详细分析此类电路的关键技术以及国内外研究团队在此类电路的研究进展与存在的问题。最后根据目前国内外研究的进展情况，分析了SPAD阵列集成读出电路的发展趋势以及各类电路存在的设计重点与难点，为SPAD阵列读出电路的设计提供一些参考。

Key technologies and development trends of SPAD array readout circuit (invited)

  Significance   In recent years, the Single Photon Avalanche Diode（SPAD） with single-photon detection capability has been widely used in weak light detection fields such as laser radar, quantum communication, fluorescence spectrum analysis and so on because of its advantages of high sensitivity, fast response, strong anti-interference ability and small size. As a new nonlinear device, SPAD detector has complex manufacturing process. In addition, various applications of SPAD array need readout integrated circuits (ROIC) for detecting sensing signals to be matched with them to achieve the extraction and processing of SPAD detector avalanche signals. Various applications have increasingly high requirements for array size, detector signal extraction and processing capabilities. At the same time, the parasitic effect, power consumption, area and other problems caused by large-scale array are becoming more and more prominent, which seriously affects the imaging quality. The design of array-type SPAD readout circuit is facing great challenges.   Progress   The readout circuit of SPAD array is mainly composed of interface circuit and signal processing circuit. The interface circuit realizes the quenching and extraction of avalanche signal, and the switching between the cut-off and the state to be measured of SPAD. It is a dynamic bias circuit. With the expansion of the array scale, it is required to add SPAD anti-bias voltage adjustable circuit in the interface circuit, realize pixel-by-pixel or regionally adjustable bias of SPAD, and SPAD high-voltage breakdown protection circuit. At present, such technology is only used in small-scale, linear array and some applications, but still cannot be realized in the application of large area array. The main difficulty is that complex circuits cannot be used due to the limitation of pixel area. According to the application of SPAD, the signal processing circuit is divided into photon timing circuit and photon counting circuit. The photon timing circuit is used to measure the flight time of photons. In the circuit, the array-type time-to-digital conversion circuit (TDC) is used. Because the arrival time of each pixel is different, each pixel needs an independent TDC, and the circuit power consumption is very high. This is also one of the reasons that limit the scale expansion of SPAD array. A related research team has proposed a TDC sharing structure, such as the Lausanne Institute of Technology in Switzerland, which proposed a TDC sharing structure (Fig.3). At the same time, because the pixel area is not limited by sharing, multi-segment TDC can be used, and the time resolution of the circuit is less than 100 ps. Compared with the photon timing circuit, the structure of the photon counting circuit is relatively simple. It only needs to record the number of photons detected in a frame. The difficulty of this kind of circuit is to effectively adjust the dead time of the SPAD detector to achieve the best compromise between the detection rate and the dark count.   Conclusions and Prospects   With the demand for SPAD large arrays and the development of readout circuits, the following development trends have emerged in relevant readout circuits in recent years: on-chip data storage, multiple echo detection of returned photon events, and free detection mode. With the further development of the application requirements of SPAD array, the readout circuit will integrate more functions, further develop towards the integration of sensing, memory and computing, and finally truly realize single-chip imaging.