全数字化PET系统时间信号基准模块设计

为了满足为全数字化PET（正电子发射断层扫描仪）系统中前端电子学模块提供时间信号基准的时钟信号的要求,采用FPGA和AD9516-4芯片设计了一种时间信号基准模块。针对时间信号基准的要求,提出了通过参考基准频率由锁相环产生高频信号,同时利用分频器实现了对高频时钟信号的分频,并用LVDS（低电压差分信号）模式对生成的多路时钟信号进行输出,从而获得了多路频率、相位、幅值均相同的同步时钟信号的方法。相比于其他方法实现的时钟分配模块,本方法具有高精确度,低功耗和高稳定性的特点。该模块已经在全数字化PET系统中使用,验证了该模块具有高精确度和高稳定性的特点。

Timing Signal Benchmark Module Design for All-Digital PET System

In order to satisfy the demand of the clock signal that provides the timing signal benchmark for the front-end electronics module of the All-Digital Positron Emission Tomography,a new kind of timing signal benchmark module is designed using FPGA and AD9516-4.In connection with the demand of the timing signal benchmark,a method is proposed.In this method,a high frequency signal is generated by the phase-locked loop through reference frequency,in the meantime,the divider in the chip is used to divide the high frequency signal,and LVDS mode is used to output the multiple clock signals,so that we can get multiple synchronous clock signals that have the same frequency,phase and amplitude.This module is already used in All-Digital PET system,and verified that this module has the characteristics of high accuracy and high stability.