实现高分辨力图像传感器高帧率输出的方法

论述了一种基于FPGA(现场可编程门阵列)的提高CMOS输出帧率的方法。高分辨力图像传感器的输出帧率只有十几帧/s甚至更低,系统将同一帧的图片重复输出,从而提高后续的输出帧率,使图像信号能够直接输出至VGA显示器。硬件电路使用图像传感器MT9D131、FPGA芯片CycloneⅡEP2C8Q208C8N和图像D/A转换芯片ADV7123组合,软件使用verilogHDL语言,将图像感应器得到的图像数据存入SDRAM(同步动态随机存储器),并将其转换为RGB格式的图像数据输出至图像D/A转换芯片ADV7123,同时在FPGA中设置写FIFO模块与读FIFO模块以避免跨越时钟域可能导致的工作不稳定的问题。

Method for achieve high frame rate output from high-resolution image sensor

A reliable and efficient design based on FPGA （field-programmable gate array） has been discussed in this paper, which will improve the output frame rate of CMOS image sensor. The output frame rate of high-resolution image sensor is only 10fps or less. Data of the same frame can be output repeatedly in this system to raise the FPS so that the image can be output to VGA （video graphics array） monitors. Image sensor MT9D131, FPGA chip, Cyclone Ⅱ EP2C8Q208C8N and ADV7123 are assemble in hardware circuit, while verilog HDL is used in software. Image data received from the sensor are saved into SDRAM （synchronous dynamic random access memory） and then converted into RGB format, in output to D/A chip ADV7123. At the same time a write-FIFO mod in FPGA should be setup to avoid the instability result of crossing the end the image data are ule and a read-FIFO module clock regions.