A 3.125-Gb/s clock and data recovery circuit for the 10-Gbase-LX4 Ethernet

A 3.125-Gb/s clock and data recovery (CDR) circuit using a half-rate digital quadricorrelator frequency detector and a shifted-averaging voltage-controlled oscillator is presented for 10-Gbase-LX4 Ethernet. It can achieve low-jitter operation and improve pull-in range without a reference clock. This CDR circuit has been fabricated in a standard 0.18-/spl mu/m CMOS technology. It occupies an active area of 0.6 /spl times/ 0.8 mm/sup 2/ and consumes 83 mW from a single 1.8-V supply. The measured bit-error rate is less than 10/sup -12/ for 2/sup 7/ - 1 PRBS 3.125-Gb/s data. It can meet the jitter tolerance specifications for the 10-Gbase-LX4 Ethernet application.