| 同步降压DC-DC转换器驱动级设计 |
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| 引用本文： | 刘焱,龚志鹏,鲍小亮,周泽坤,张波. 同步降压DC-DC转换器驱动级设计[J]. 微电子学, 2012, 42(2): 187-190,194 |
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| 作者姓名： | 刘焱 龚志鹏 鲍小亮 周泽坤 张波 |
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| 作者单位： | 电子科技大学 电子薄膜国家重点实验室,成都,610054 |
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| 摘 要： | 提出一种输入电压为4.5～23 V、输出电流可达3A的同步降压转换器的驱动级,内部集成了电平移位、死区时间控制及同步管反向电流限制等功能.设计了一种为内部逻辑供电的低压电源,使驱动级大部分可以由低压器件构成,与外部电源供电的驱动级相比,大大减小了芯片面积.分析了该电路的结构与工作原理；采用0.6 μm BCD工艺,通过HSPICE进行仿真,证明该驱动级方案切实可行.
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| 关 键 词： | 同步降压 DC-DC转换器 电平位移 死区时间 LDO |
Design of Gate Driver for Synchronous Step-Down Converter |
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| LIU Yan , GONG Zhipeng , BAO Xiaoliang , ZHOU Zekun , ZHANG Bo. Design of Gate Driver for Synchronous Step-Down Converter[J]. Microelectronics, 2012, 42(2): 187-190,194 |
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| Authors: | LIU Yan GONG Zhipeng BAO Xiaoliang ZHOU Zekun ZHANG Bo |
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| Affiliation: | (State Key Laboratory of Electronic Thin Films and Integrated Devices,Univ.of Elec.& Sci.Technol.of China,Chengdu 610054,P.R.China) |
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| Abstract: | A gate driver was designed for synchronous step-down DC/DC converter,which could deliver up to 3 A output current from 4.5 V to 23 V input supply.Level shifter,adverse current limit of low side power MOSFETs and dead time control modules were incorporated into the circuit.Low-voltage power supply was designed for internal logic modules,so that the driver could be constructed mostly with low voltage devices.Compared with external supply powered driver,the proposed circuit occupies a much smaller chip area.Circuit structure and its operational principle were analyzed.HSPICE simulation based on 0.6 μm BCD process validated design of the gate driver. |
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| Keywords: | Synchronous step-down DC/DC converter Level shifter Deadzone time LDO |
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