JPEG2000中高速Tier1编码器的VLSI设计

提出并实现了一种用于JPEG2000编码芯片中高速Tier1编码器的并行流水结构。该编码器采用了双位平面并行编码、通道扫描的流水控制、状态变量实时产生电路以及列内并行上下文生成等技术,实现了一种0状态存储器的多并行流水位平面编码器;并行同步流水的多记号输入算术编码器以及不定算术编码周期下的多输入同步读取电路,使算术编码速度平均为1.3上下文编码记号对/时钟;对算术编码产生的压缩码流存储呈高效的宏流水线结构。该编码器在100MHz工作时钟下,最高编码速度为85M小波系数/s。用SMIC0.25μm工艺库综合时,门电路为6.3万门,片上存储器为26kb(码块大小32×32),关键路径为5.2ns。

VLSI Design of High-speed Tier1 Encoder of JPEG2000

A parallel and pipeline architecture of Tier1 encoder is proposed for JPEG2000 encoder chip. Multiple parallel and pipeline methods are adopted in a bit-plane encoder (BPE) with zero state variables′ storing memory, such as dual bit-plane parallel encoding, pipeline control in pass scan, concurrent state variable′s generation circuit and parallel context formation inside a column. An arithmetic encoder (AE) for multi-symbol input is implemented with parallel and pipeline architecture; synchronous accessing circuit for input-symbols is also designed for variable arithmetic encoding cycles; they make coding pairs of CX/D up to 1.3 pair/cycle on average. Memory storing for compressed code from arithmetic encoder is efficiently implemented as macro pipeline. The Tier1 encoder′s maximum rate is up to 85 M wavelet coefficients per-second at 100 MHz. Synthesized with SMIC 0.25 μm library in Synopsys DC, the equivalent gates of NAND2 are about 63 K,there is 26 Kb on-chip memory (code block size 32×32) and the critical path is 5.2 ns.