面向阵列处理器的分布式共享存储结构设计

为了缓解随处理器核数增多而被激化的“存储墙”问题,提出了局部高速交叉互连、全局片上网络互连的两级混合互连网络结构,设计了支持统一编址方式的数据传送机制.在现场可编程门阵列上实现了2种规模的存储结构,对面积、时序和功耗进行统计.基于SystemC开发了混合仿真平台,仿真结果表明,所提结构具有较高的存储访问带宽和较低的局部数据访问延迟.

Design of Distributed Shared Memory Structure for Array Processor

With the increasing of number of processors,the problem of memory wall was more severely.In order to alleviate this problem,two-level mixed interconnection network was proposed:fast crossbar for local data transfer and network on chip for long distance data communication.Meanwhile data transfer mechanism was designed to support unified addressing.Two memory architecture sizes were implemented on field rpogrammable gate array,and area,frequency and power consumption were evaluated.A mixed simulation testbench based on SystemC language was developed.The simulation results show that the designed architecture has higher memory access bandwidth and lower local accessing latency.