QDR SRAM控制器的设计与FPGA实现

介绍一种新型静态存储器——QDR（Quad Data Rate）SRAM的存储器结构、与系统的接口连接、主要的操作时序。参考实际QDR存储器内部组成。利用FPGA实现存储器控制器的设计实现。旨在通过FPGA的快速、灵活、容易修改的特点，设计并实现在高速数据通信系统中，QDR静态存储器用于处理器和接口连接的外设之间的数据交换。着重分析QDR控制器的读／写操作状态机。

Design of QDR SRAM Controller and Realization of FPGA

This article introduces the memory architecture and timing operation of a new architectures static memorynamed QDR （Quad Data Rate）SRAM. With the internal architecture of a QDR and FPGA, the design of QDR controller is achieved. The purpose of the article is designing and carrying out the QDR using FPGA which is a high speed and easy modifying. The QDR links the processor and interface which are both in the high speed data communication system. The article also introduces the state machine of QDR controller＇s read ＆ writes operations.