一种用于MPEG2解码芯片的高效内存存储结构

为了提高MPEG2解码芯片的内存带宽利用率,根据SDRAM的固有特征和MPEG2解码时对内存读取的特点,提出了一种新的内存存储结构。采用该方法,可以大大减少内存读写的冗余时间,从而满足MPEG2 MP@HL解码器的设计要求。与直接映射相比,文章提出的方法可以使行激活的次数至少减少82.6%,内存读写时间减少59%以上。

A High-Performance Memory Storage Architecture for MPEG2 Decoder

To improve the memory bandwidth in MPEG2 decoder,a new memory storage architecture was proposed,which was based on the inherent features of SDRAM and the characteristics of MPEG2 decoder in memory access.Using this architecture,the number of overhead cycles needed for row-activations in SDRAM can be minimized to satisfy the design requirements for MPEG2 MP@HL decoder.It is demonstrated that the proposed method can reduce about 90% of row activations and 60% of the cycles needed for decoding,compared with linear translation.