Degradation of double-gate polycrystalline silicon TFTs due to hot carrier stress

Degradation phenomena due to hot carrier stress conditions were investigated in double-gate polysilicon thin film transistors fabricated by sequential lateral solidification (SLS). We varied the hot carrier stress conditions at the front gate channel by applying various voltages at the back-gate. Thus, we investigated the device electrical performance under such stress regimes. As a conclusion, we demonstrate that severe degradation phenomena may occur at the back polysilicon interface depending on the back-gate voltage during stress. The nature of these phenomena becomes evident when the back-gate bias is such that the back interface is coupled or decoupled from the front gate electrical characteristics.