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面向AADL模型的存储资源约束可调度性分析
引用本文:陆寅,秦树东,习乐琪,董云卫. 面向AADL模型的存储资源约束可调度性分析[J]. 软件学报, 2021, 32(6): 1663-1681
作者姓名:陆寅  秦树东  习乐琪  董云卫
作者单位:西北工业大学计算机学院,陕西西安 710072;西北工业大学软件学院,陕西西安 710072
基金项目:国家自然科学基金(61772423)
摘    要:嵌入式实时系统在安全关键领域变得越来越重要,其广泛应用于航空航天.汽车电子等具有严格时间约束的实时系统中.随着嵌入式系统的复杂度越来越高,在系统开发的早期设计阶段就需要对其可调度性进行分析评估.系统中的存储资源会对可调度性产生一定影响,在抢占式实时嵌入式系统引入缓存后,任务的最坏执行时间可能发生变化.因此,分析缓存相关...

关 键 词:软件架构分析与设计语言AADL  复杂嵌入式系统  缓存相关抢占延迟  资源约束的可调度性
收稿时间:2020-08-31
修稿时间:2020-10-26

On Schedulability Analysis of AADL Architecture with Storage Resource Constraint
LU Yin,QIN Shu-Dong,XI Le-Qi,DONG Yun-Wei. On Schedulability Analysis of AADL Architecture with Storage Resource Constraint[J]. Journal of Software, 2021, 32(6): 1663-1681
Authors:LU Yin  QIN Shu-Dong  XI Le-Qi  DONG Yun-Wei
Affiliation:School of Computer Science, Northwest Polytechnical University, Xi''an 710072, China;School of Software Engineering, Northwest Polytechnical University, Xi''an 710072, China
Abstract:The embedded system has been wildly applied in real-time automatic control systems, and most of these systems are safety-critical. For example, the engine control systems in an automobile, and the avionics in an airplane. It is very important to verify the schedulability property of such real-time embedded system in its early design stages, so that to avoid unexpected loss for the debugging of architecture design frictions. However, it has been proved to be a tough challenge to evaluate the schedulabiligy of a PSRT (preemptive-scheduling real-time) system, especially when taking into consideration the constraints of system resources. The cache memory build inside the processor is such a kind of exclusive-accessing resource that is shared by all the tasks deployed on the processor. And the CPRD (Cache-related PReemption Delay) caused by preemptive task scheduling will bring extra time to the execution time to all the tasks. Thus the CPRD should be taken into consideration when estimating the WCET (Worst Case Executing Time) of tasks in a real-time system. A model-based architecture level schedulability evaluate and verification method, which is designed for priority based PSRT system, is proposed in this paper, in order to do cache resource constrained, and CPRD related schedulability evaluation based on AADL system architecture model. In the first step, the paper enhances the property set of AADL storage elements, so that to be compatible with cache memory properties in system architecture model constructing; Secondly, the paper proposes a set or algorithms to:1) estimate the CPRDs of a task before it is completed; 2) do system schedule simulation and construct the schedule sequence with the constraint of Cache resource and CPRDs involved; 3) WCET estimation of the tasks in such a CPRD considered, preemptive-scheduling execution sequence. And finally, methods mentioned above are implemented within a prototype software toolkit, which is designed to do system level schedulability evaluation and verification with CPRD constraints considered. The toolkit is tested with a use case of aircraft airborne open-architecture intelligent information system. The result shows that, compared with schedule sequence constructed without Cache memory resource constraints, the WCET estimated for most tasks are extended, and sequence order is changed. In some extreme cases, when CPRD is taken into consideration, some task is evaluated to be incompletable. The use case test shows that the method and algorithms proposed in this paper is feasible.
Keywords:AADL  complex embedded system  Cache Related Preemption Delay  Resource Constraint Schedulability
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