Dynamic-type CMOS four-valued logic circuits |
| |
Authors: | TATSUKI WATANABE MASAYUKI MATSUMOTO SHIGENORI NAGARA |
| |
Affiliation: | 1. Department of Electrical Engineering, Faculty of Engineering , Toyo University , Kawagoe-Shi, Saitama Pref., 350 Japan;2. NEC Corporation , Abiko-Shi, Chiba, 270 Japan |
| |
Abstract: | We first briefly introduce the various kinds of basic CMOS four-valued logic circuit that can be suitably employed for circuits with clock pulses. Using these, the design of multiple-valued MAX and MIN circuits with many inputs, each of which has two quaternary figures, are developed. It is shown that the number of MOS transistors required for these circuits can be reduced in comparison to binary circuits having equivalent functions. Successful simulation results using SPICE-2 for the circuit operations are given. |
| |
Keywords: | |
|
|