STI process steps for sub-quarter micron CMOS |
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| Authors: | P Sallagoity F Gaillard M Rivoire M Paoli M Haond S McClathie |
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| Affiliation: | aFrance Telecom-CNET, B.P. 98, 38243 Meylan Cedex, France;bElectrotech, Thornbury Labs, Littleton-upon-Severn, Bristol BS12 1NP, UK |
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| Abstract: | This paper presents Shallow Trench Isolation (STI) process steps for sub-1/4 μ CMOS technologies. Dummy active areas, vertical trench sidewalls, excellent gap filling, counter mask etch step and CMP end point detection, have been used for a 0.18 μm CMOS technology. Electrical results obtained with a 5.5 nm gate oxide thickness show good isolation down to 0.3 μm spacing. Good transistor performances have been demonstrated. |
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| Keywords: | CMOS integrated circuits Etching Microelectronic processing Masks Gates (transistor) Shallow trench isolation (STI) |
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