| 基于FPGA的幅值可调信号发生器设计 |
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| 引用本文： | 张有志,张鹍.基于FPGA的幅值可调信号发生器设计[J].电子设计工程,2011,19(9):115-117,120. |
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| 作者姓名： | 张有志 张鹍 |
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| 作者单位： | 1. 山东凯文科技职业学院,山东,济南,250200
2. 北京邮电大学,信息与通信工程学院,北京,100876 |
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| 摘 要： | 针对信号发生器对输出频率精度高和幅值可调的要求,采用直接数字频率合成(DDS)技术,提出一种基于FP-GA的幅值、频率均可调的、高分辨率、高稳定度的信号发生器设计方案。采用AT89S52单片机为控制器,控制FPGA产生波形的数字信号,结合双数模(D/A)转换器及低通滤波器,最终实现输出信号幅值0～5 V可调,分辨率为10 bits;频率范围1 Hz～10 MHz可调,最小分辨率为1 Hz;频率稳定度优于10-4。信号参数可通过键盘进行设置,并在LCD上输出。由于FPGA的可编程性,易于对系统进行升级和优化。
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| 关 键 词： | FPGA 信号发生器 DDS 单片机 VHDL |
Design of amplitude adjustable signal generator based on FPGA |
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| ZHANG You-zhi,ZHANG Kun.Design of amplitude adjustable signal generator based on FPGA[J].Electronic Design Engineering,2011,19(9):115-117,120. |
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| Authors: | ZHANG You-zhi ZHANG Kun |
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| Affiliation: | 1.Shandong Kaiwen College of Science & Technology,Ji’nan 250200,China;2.School of Information and Communication Engineering,Beijing University of Posts Telecommunications,Beijing 100876,China) |
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| Abstract: | For the requirements of high frequency accuracy and amplitude adjustability of a signal generator,the direct digital synthesis(DDS) technology is applied in the design of the FPGA-based signal generator.The amplitude and frequency of the output of the signal generator are adjustable,and high resolution and high stability are obtained.MCU AT89S52 is used to control the whole system,and the signal generated by FPGA is output through a double-DAC and a low-pass filter.The amplitude range is 0~5 V with the resolution of 10-bit,the frequency range is 1 Hz~10 MHz with the minimum resolution of 1 Hz,and the frequency stability is better than 10-4.The parameters of amplitude and frequency can be entered through keyboard and displayed on LCD.Due to the programmability of FPGA,the system is easy to upgrade and optimize.full adder function can be well implemented by using simulation design of Multisim software. |
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| Keywords: | FPGA signal generator DDS MCU VHDL |
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