| 基于CPLD的CCD相机数据存储的时序设计 |
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| 引用本文： | 陈琦,李露瑶.基于CPLD的CCD相机数据存储的时序设计[J].现代电子技术,2008,31(18). |
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| 作者姓名： | 陈琦 李露瑶 |
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| 作者单位： | 1. 西安文理学院,陕西,西安,710068
2. 中国科学院西安光学精密机械研究所,陕西,西安,710068 |
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| 摘 要： | 介绍采用美国SMD公司的4M4CCD相机设计的空间成像系统的组成结构,重点介绍基于CPLD的CCD相机数据存储的时序设计。在设计中选用复杂可编程逻辑器件CPLD作为硬件设计平台,采用硬件描述语言VHDL编程实现,产生CCD相机存储所采集图像数据的存储器工作所需要的时序信号,在通过Max PlusⅡ环境下进行仿真验证后,设计的时序电路下载到CPLD器件中。经CCD相机系统成像验证该设计满足技术要求。
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| 关 键 词： | CCD相机 CPLD 时序电路 VHDL |
Time Sequence Design of CCD Camera's Data Memory Based on CPLD |
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| CHEN Qi,LI Luyao.Time Sequence Design of CCD Camera''s Data Memory Based on CPLD[J].Modern Electronic Technique,2008,31(18). |
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| Authors: | CHEN Qi LI Luyao |
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| Abstract: | CCD camera is one of the most widely used optic senser,space image system is designed by using 4M4CCD camera of SMD Company,the composition of system is introduced.Especially the time sequence design of CCD camera data memory.In the design,Complex Programmable Logic Device(CPLD) is chosen as the hardware design platform,writing program by adopting hardware describing language VHDL,producing the time sequence signal is provided for data memory,time sequence generator successfully fulfilled system simulation with MAXplusII software and fitted into EPM7064.The result indicates that the design of time sequence generator can fit the technology demand. |
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| Keywords: | CCD camera CPLD time sequence circuit VHDL |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
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