| 适用于多核处理器的扩展寄存器文件设计 |
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| 引用本文： | 肖瑞瑾,权衡,张家杰,尤凯迪,英彦,虞志益. 适用于多核处理器的扩展寄存器文件设计[J]. 计算机工程, 2012, 38(15): 283-285,289 |
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| 作者姓名： | 肖瑞瑾 权衡 张家杰 尤凯迪 英彦 虞志益 |
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| 作者单位： | 复旦大学专用集成电路与系统国家重点实验室 上海201203 |
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| 基金项目： | 上海市科委集成电路专项基金资助项目，复旦大学专用集成电路与系统国家重点实验室基金资助项目 |
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| 摘 要： | 针对处理器中可用寄存器数量有限的问题，提出一种适用于多核处理器的扩展寄存器文件设计方案。采用多组结构进行硬件设计，将通信端口映射在扩展寄存器地址空间上，以实现寄存器寻址核间通信机制，引入兼具底层指令与高层封装的混合软件配置方案，改进软件编译流程。评估结果表明，该方案将可用寄存器文件的数量增加一倍，核间通信指令数目减少50%，系统吞吐率得到优化。
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| 关 键 词： | 扩展寄存器 多组结构 多核处理器 核间通信 LDPC译码器 |
| 收稿时间： | 2011-10-08 |
Design of Extended Register File for Multi-core Processor |
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| XIAO Rui-jin , QUAN Heng , ZHANG Jia-jie , YOU Kai-di , YING Yan , YU Zhi-yi. Design of Extended Register File for Multi-core Processor[J]. Computer Engineering, 2012, 38(15): 283-285,289 |
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| Authors: | XIAO Rui-jin QUAN Heng ZHANG Jia-jie YOU Kai-di YING Yan YU Zhi-yi |
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| Affiliation: | (State Key Laboratory of Application Specific Integrated Circuit & System,Fudan University,Shanghai 201203,China) |
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| Abstract: | Concerning the issue of limited number of register files in processor,this paper presents an extended register file design scheme for multi-core processors.A multi-bank architecture is employed for hardware design,and the communication ports are mapped in the address space of extended register file,which enables an inter-core communication method with register file direct addressing.A hybrid software configuring method is proposed with both bottom-layer instructions and top-layer packaged functions,and the compiling flow is improved.Estimation result shows this scheme can both double the number of available register files and reduce the number of instructions for inter-core communication by 50%.And the system throughput is optimized. |
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| Keywords: | extended register multi-bank architecture multi-core processor inter-core communication LDPC decoder |
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