| A 10-20 Gb/s PAM2-4 transceiver in 65 nm CMOS |
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| 作者姓名： | 高茁 杨袆 钟石强 杨旭 黄令仪 胡伟武 |
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| 作者单位： | Institute;Computing;Technology;Chinese;Academy;Sciences;Graduate;University; |
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| 摘 要： | This paper presents the design of a 10 Gb/s PAM2, 20 Gb/s PAM4 high speed low power wire-line transceiver equalizer in a 65 nm CMOS process with 1 V supply voltage. The transmitter occupies 430 × 240 μm2 and consumes 50.56 mW power. With the programmable 5-order pre-emphasis equalizer, the transmitter can compensate for a wide range of channel loss and send a signal with adjustable voltage swing. The receiver equalizer occupies 146 × 186μm^2 and consumes 5.3 mW power.
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| 关 键 词： | 脉幅调制 发电站 电源电压 均衡器 供电系统 |
A 10-20 Gb/s PAM2-4 transceiver in 65 nm CMOS |
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| Gao Zhuo,Yang Yi,Zhong Shiqiang,Yang Xu,Huang Lingyi, Hu Weiwu.A 10-20 Gb/s PAM2-4 transceiver in 65 nm CMOS[J].Chinese Journal of Semiconductors,2009(1):54-58. |
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| Authors: | Gao Zhuo Yang Yi Zhong Shiqiang Yang Xu Huang Lingyi Hu Weiwu |
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| Affiliation: | 1 Institute of Computing Technology;Chinese Academy of Sciences;Beijing 100083;China;2 Graduate University of the Chinese Academy of Sciences;Beijing 100049;China |
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| Abstract: | serial link PAM equalizer pre-emphasis CTLE |
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| Keywords: | serial link PAM equalizer pre-emphasis CTLE |
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