| 面向SOPC的异构IP快速集成 |
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| 引用本文： | 周学功,梁樑,周博,彭澄廉.面向SOPC的异构IP快速集成[J].计算机辅助设计与图形学学报,2006,18(12):1844-1849. |
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| 作者姓名： | 周学功 梁樑 周博 彭澄廉 |
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| 作者单位： | 复旦大学计算机与信息技术系,上海,200433 |
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| 摘 要： | 设计并实现了一个片上可编程系统（SOPC）设计工具ESIGE，它通过开放式的结构对不同来源的异构软核IP进行封装，对SOPC设计人员屏蔽了IP的复杂性．不同实现方式和不同总线接口的IP可以混合使用．ESIGE通过层次化的集成和灵活的IP互连方式支持复杂的IP互连结构，利用虚拟设计和自动化的IP集成显著地降低了SOPC设计的工作量．
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| 关 键 词： | IP集成 片上可编程系统 嵌入式系统 快速样机平台 |
| 收稿时间： | 2006-01-25 |
| 修稿时间： | 2006-06-19 |
Fast Heterogeneous IP Integration for SOPC Design |
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| Zhou Xuegong,Liang Liang,Zhou Bo,Peng Chenglian.Fast Heterogeneous IP Integration for SOPC Design[J].Journal of Computer-Aided Design & Computer Graphics,2006,18(12):1844-1849. |
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| Authors: | Zhou Xuegong Liang Liang Zhou Bo Peng Chenglian |
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| Affiliation: | Department of Computing and Information Technology, Fudan University, Shanghai 200433 |
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| Abstract: | A system on a programmable chip (SOPC) design tool called ESIGE is presented. It provides an open structure that encapsulates heterogeneous soft IP cores from different providers, and hides the complexity of IP cores from the SOPC designers. IP cores with different implementation techniques and different bus interfaces can be integrated together. ESIGE integrates IP cores in a hierarchical and flexible way, supports complex integration structure. With virtual design and automatic IP integration, ESIGE reduces the complexity of SOPC design significantly. |
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| Keywords: | IP integration system on a programmable chip embedded system rapid prototyping platform |
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