基于FPGA的并行多发可编程解析器

传统的报文解析器解析的协议类型和协议层次固定,缺乏对新网络协议的支撑,限制了网络设备的可编程性。抽象出形式化的解析流程,并基于FPGA实现协议无关的可编程解析器,对新协议的支撑无需更改硬件,仅需要重新映射解析图。基于该机制,引入一系列优化技术,克服了包解析固有的串行性,节约了存储资源,为实现高速的可编程报文解析提供了有效的解决方案。基于通用多核和高性能FPGA实验平台,进行了硬件代价和性能的评估。实验结果表明,采用可编程解析器能大幅提升报文解析性能,实现了通用网络协议及潜在的网络协议快速的解析,可有效地支持快速的定制网络协议发展。

A Multi-concurrent programmableparser based on FPGA

The protocol type and level of traditional packet parser are fixed, which lacks support for the new network protocols, and restricts the programmability of network devices. We abstract the formalization of the parsing process and implement a protocol independent programmable parser based on the FPGA. The support for the new protocol does not require hardware changes, except remapping the parsing graph. Based on this mechanism, a series of optimization techniques are introduced to overcome the inherent serialization of packet parsing, save storage resources, and provide an effective solution to the realization of high speed programmable message parsing. We evaluate hardware cost and performance on the platform of general purpose multi core and high performance FPGA. Experimental results show that the programmable parser can greatly improve the performance of message parsing, quickly analyze general network protocols and potential network protocols, and effectively support the rapid development of customized network protocols.