| 基于扩展汉明码的BISR设计优化 |
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| 引用本文： | 沙亚兵,李文石.基于扩展汉明码的BISR设计优化[J].微电子学与计算机,2011,28(12):92-95. |
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| 作者姓名： | 沙亚兵 李文石 |
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| 作者单位： | 1. 苏州大学电子信息学院,江苏苏州215001／雄立科技苏州有限公司,江苏苏州215021
2. 苏州大学电子信息学院,江苏苏州,215001 |
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| 基金项目： | 江苏省高校自然科学研究项目资助(09KJB510017) |
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| 摘 要： | BISR本质是自动实现电路内部纠错.为监督SARM中的176bit宽并行数据,提出一种基于扩展汉明码设计BISR电路的优化技术.将并行数据劈裂为两个模块,分别利用基于扩展汉明码的独立ECC,组建BISR架构.根据异或逻辑的可交换性,重排子运算项,建立XOR-Tree可合并项的特征图,观察与提取可以共用的子运算项,借助这种＂兼容＂策略优化XOR-Tree,在TSMC 90nm工艺中满足了降低时延和面积的工程要求.仿真结果显示,时延与面积分别降低了约28%和约35%,功耗降低约36%.最终时延为1.5ns,面积为6 200μm^2,功耗是0.54mW,表明了本优化方法的有效性.
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| 关 键 词： | BISR ECC XOR-Tree 时延 面积 功耗 |
BISR Design Optimization Based on Extended Hamming Code |
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| SHA Ya-bing,LI Wen-shi Co.,Ltd.,Suzhou ,China.BISR Design Optimization Based on Extended Hamming Code[J].Microelectronics & Computer,2011,28(12):92-95. |
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| Authors: | SHA Ya-bing LI Wen-shi Co Ltd Suzhou China |
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| Affiliation: | SHA Ya-bing1,2,LI Wen-shi1(1 School of Electronics and Information,Soochow University,Suzhou 215006,China,2 XeL Technology(Suzhou) Co.,Ltd.,Suzhou 215021,China) |
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| Abstract: | BISR is to achieve the internal nature of the automatic correction function.In order to supervise SRAM's 176-bit wide parallel data,this paper proposed a method to optimize the BISR which based on extended hamming code.The data has been split into two parts suit for ECC architecture.Under the exchangeable logic terms,we built a Signature-map for XOR-Tree.In TSMC 90nm process the results met the project requirements showing reduced 28% of delay,35% of area and 36% of power.At last,ECC delay is 1.5 ns,area,6 ... |
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| Keywords: | BISR ECC XOR-Tree delay area power dissipation EEACC: B10 |
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