| Influence of layout parameters on snapback characteristic for a gate-grounded NMOS device in 0.13-μm silicide CMOS technology |
| |
| 引用本文： | 姜玉稀,李娇,冉峰,曹家麟,杨殿雄.Influence of layout parameters on snapback characteristic for a gate-grounded NMOS device in 0.13-μm silicide CMOS technology[J].半导体学报,2009,30(8):82-89. |
| |
| 作者姓名： | 姜玉稀 李娇 冉峰 曹家麟 杨殿雄 |
| |
| 作者单位： | Microelectronic;Research;Development;Center;Shanghai;University; |
| |
| 基金项目： | supported by the National Natural Science Foundation of China(Nos.60773081,60777018);;the AM Foundation by Science and Technology Commission of Shanghai Municipality(No.087009741000);;the SDC Project by Science and Technology Commission of Shanghai Municipality(Nos.08706201800,077062008,08706201000) |
| |
| 摘 要： | Gate-grounded NMOS （GGNMOS） devices with different device dimensions and layout floorplans have been designed and fabricated in 0.13-μm silicide CMOS technology. The snapback characteristics of these GGN-MOS devices are measured using the transmission line pulsing （TLP） measurement technique. The relationships between snapback parameters and layout parameters are shown and analyzed. A TCAD device simulator is used to explain these relationships. From these results, the circuit designer can predict the behavior of the GGNMOS devices under high ESD current stress, and design area-efficient ESD protection circuits to sustain the required ESD level. Optimized layout rules for ESD protection in 0.13-μm silicide CMOS technology are also presented.
|
| 关 键 词： | CMOS技术 NMOS器件 硅化物 影响参数 回溯 ESD保护电路 GGNMOS 特性 |
Influence of layout parameters on snapback characteristic for a gate-grounded NMOS device in 0.13-μm silicide CMOS technology |
| |
| Jiang Yuxi,Li Jiao,Ran Feng,Cao Jialin, Yang Dianxiong.Influence of layout parameters on snapback characteristic for a gate-grounded NMOS device in 0.13-μm silicide CMOS technology[J].Chinese Journal of Semiconductors,2009,30(8):82-89. |
| |
| Authors: | Jiang Yuxi Li Jiao Ran Feng Cao Jialin Yang Dianxiong |
| |
| Affiliation: | Microelectronic Research & Development Center;Shanghai University;Shanghai 200072;China |
| |
| Abstract: | electrostatic discharge gate-grounded NMOS snapback characteristic layout parameters |
| |
| Keywords: | electrostatic discharge gate-grounded NMOS snapback characteristic layout parameters |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
| 点击此处可从《半导体学报》浏览原始摘要信息 |
|
点击此处可从《半导体学报》下载全文 |
