前向纠错技术中卷积交织器的FPGA实现

介绍了信道编码中所采用的前向纠错编码（FEC）方案中的重要技术——卷积交织器和解交织器的原理，并在此基础上提出了基于FPGA的卷积交织器的设计方案。丈中对卷积交织器设计的关键部分，即读写地址的产生方法进行了详细分析，给出了一种新的地址计算方法，并通过对FPGA内部EAB资源的双口RAM的存储单元的读写操作的合理控制，实现了卷积交织。该设计具有实现简单、占硬件资源少等优点。

FPGA Implementation of Interleaver in Forward Error Correction Technique

This paper presents the theory of an important technology, that is, the interleaver and deinterleaver used in the forward error correction for channel coding, and proposes an interleaver design based on FPGA. The key point of the design the way for reading and writing address, is analyzed in detail. A new method to calculate the address is given, and the implementation of interleaver is realized by properly controlling the operation of reading and writing of dual-port RAM, which is the EAB resource in FPGA chip. The design has advantages of easy realization and less resource consumption.