基于动态局部重构的自重构系统设计

基于EAPR(early access partial reconfiguration)动态部分重构(dynamic partial reconfiguration,DPR)方法,研究了在 FPGA上实现自重构嵌入式系统的设计方法。该方法运用 Xilinx的 ISE12.4开发工具,调用已有 IP 核,搭建包含用户定制IP核的自重构嵌入式系统硬件平台,并在Virtex5 FPGA上验证。设计中运用了二维重构技术,划分了3个可重构区域,每个区域包含4个可重构模块。本设计方法可以降低嵌入式系统开发复杂度、提高系统灵活性、降低开发成本、缩短开发周期以及减少系统功耗。

Design of self reconfigurable system based on DPR

On the basis of Dynamic Partial Reconfiguration (DPR) method Early Access Partial Reconfiguration (EAPR), design method of self reconfiguration embedded system implemented on FPGA is studied. The hardware platform of the embedded system containing a custom made IP is built by integrating merchant IPs resorting to the development tool ISE12.4 provided by Xilinx. Two dimension reconfiguration technology is used in the design of the system which includes three Reconfigurable Partitions (RPs) and four Reconfigurable Modules (RMs) are available to each RP. Afterward, it is implemented on Virtex5 FPGA to verify the feasibility of the method. Via this method, the development complexity is reduced while development flexibility is improved, achieving lower cost, less time to market and power consumption reduction.