IR thermography and FEM simulation analysis of on-chip temperature during thermal-cycling power-metal reliability testing using in situ heated structures |
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| Authors: | Helmut Kck Vladimir Ko&#x;el Christian Djelassi Michael Glavanovics Dionyz Pogany |
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| Affiliation: | aKAI (Kompetenzzentrum Automobil-und Industrie-Elektronik), Europastrasse 8, 9524 Villach, Austria;bInstitute for Solid State Electronics, Vienna University of Technology, Floragasse 7-1, 1040 Vienna, Austria;cFaculty of Electrical Engineering and Information Technology, Slovak University of Technology, Ilkovičova 3, 81219 Bratislava, Slovak Republic |
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| Abstract: | A calibrated system for power metal reliability analysis in smart power technology chips is presented. This system is mainly designed for temperature evaluation during temperature-cycling experiments. Infrared camera measurements under single shot high energy pulses are correlated with electro-thermal finite element simulation and failure analysis. A special test structure, containing poly-silicon heaters, is used to produce thermal stress. The location of a hot spot agrees well with the position of degraded power metal. |
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