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异质栅全耗尽应变硅金属氧化物半导体模型化研究
引用本文:曹磊,刘红侠,王冠宇.异质栅全耗尽应变硅金属氧化物半导体模型化研究[J].物理学报,2012,61(1):17105-017105.
作者姓名:曹磊  刘红侠  王冠宇
作者单位:西安电子科技大学微电子学院,宽禁带半导体材料与器件教育部重点实验室, 西安 710071
基金项目:国家自然科学基金(批准号:60976068, 60936005)和 教育部科技创新工程重大项目培育基金(批准号:708083)资助的课题.
摘    要:为了进一步提高小尺寸金属氧化物半导体(MOSFET)的性能,在应变硅器件的基础上, 提出了一种新型的异质栅MOSFET器件结构.通过求解二维Poisson方程,结合应变硅技术的物理原理,建立了表面势、表面电场以及阈值电压的物理模型,研究了栅金属长度、功函数以及双轴应变对其的影响. 通过仿真软件ISE TCAD进行模拟仿真,模型计算与数值模拟的结果基本符合. 研究表明:与传统器件相比,本文提出的异质栅应变硅新器件结构的载流子输运效率进一步提高, 可以很好地抑制小尺寸器件的短沟道效应、漏极感应势垒降低效应和热载流子效应, 使器件性能得到了很大的提升. 关键词: 应变硅 异质栅 阈值电压 解析模型

关 键 词:应变硅  异质栅  阈值电压  解析模型
收稿时间:2011-02-23

Study of modeling for hetero-materiel gate fully depleted SSDOI MOSFET
Cao Lei,Liu Hong-Xia and Wang Guan-Yu.Study of modeling for hetero-materiel gate fully depleted SSDOI MOSFET[J].Acta Physica Sinica,2012,61(1):17105-017105.
Authors:Cao Lei  Liu Hong-Xia and Wang Guan-Yu
Affiliation:Key Laboratory of Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices, School of Microelectronics, Xidian University, Xi'an 710071, China;Key Laboratory of Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices, School of Microelectronics, Xidian University, Xi'an 710071, China;Key Laboratory of Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices, School of Microelectronics, Xidian University, Xi'an 710071, China
Abstract:In this paper,we propose a new device structure called HMG SSDOI (hetero-materiel gate strained Si directly on insulator), which combines the advantages of strained-silicon and hetero-material gate technology. By solving 2D Poisson's equation, we present models of the surface potential, surface electric field and threshold voltage for the new structure. These models take into account the effects of the gate length, the work function and the energy band. ISE TCAD is also used to simulate the performance of new device structure. The comparison results of model calculation and mathematic simulation show that the new structure of HMG SSDOI can enhance the carrier transport efficiency and suppress short channel effect, drain induction barrier lower and hot carrier effect, which improves device performance greatly.
Keywords:strained Si  hetero-material gate  threshold voltage  analytical model
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