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基于重用信息的非易失性缓存动态旁路策略
引用本文:焦童,陈玲玲,安鑫,李建华. 基于重用信息的非易失性缓存动态旁路策略[J]. 计算机工程, 2021, 47(4): 158-165. DOI: 10.19678/j.issn.1000-3428.0057507
作者姓名:焦童  陈玲玲  安鑫  李建华
作者单位:合肥工业大学 计算机与信息学院, 合肥 230009
基金项目:中央高校基本科研业务费专项资金;国家自然科学基金
摘    要:非易失性存储器具有能耗低、可扩展性强和存储密度大等优势,可替代传统静态随机存取存储器作为片上缓存,但其写操作的能耗及延迟较高,在大规模应用前需优化写性能.提出一种基于缓存块重用信息的动态旁路策略,用于优化非易失性存储器的缓存性能.分析测试程序访问最后一级缓存(LLC)时的重用特征,根据缓存块的重用信息动态预测相应的写操...

关 键 词:非易失性存储器  多核处理器  缓存  重用信息  旁路策略  能耗
收稿时间:2020-02-26
修稿时间:2020-05-06

Reuse Information-based Dynamic Bypass Policy for Non-Volatile Cache
JIAO Tong,CHEN Lingling,AN Xin,LI Jianhua. Reuse Information-based Dynamic Bypass Policy for Non-Volatile Cache[J]. Computer Engineering, 2021, 47(4): 158-165. DOI: 10.19678/j.issn.1000-3428.0057507
Authors:JIAO Tong  CHEN Lingling  AN Xin  LI Jianhua
Affiliation:School of Computer and Information, Hefei University of Technology, Hefei 230009, China
Abstract:Non-Volatile Memory(NVM)has the advantages of low energy consumption,strong scalability and high storage density.It can replace the traditional Static Random Access Memory(SRAM)as on-chip cache,but is also faced with high energy consumption and delay for write operations,so it is necessary to optimize the write performance for large-scale application.This paper proposes a dynamic bypass policy based on cache block reuse information to optimize the cache performance of NVM.It analyzes the reuse characteristics of the test program accessing the Last-Level Cache(LLC).According to the reuse information of the cache block,it dynamically predicts whether the corresponding write operation bypasses the non-volatile cache and completes the filling when LLC is missing using the bypass operation of the prediction table.At the same time,it adopts the dynamic path selection to carry out the upper level cache write back operation,and select the appropriate upper level cache for the bypass cache block through the monitoring module.The cache blocks that are frequently reused are filled into the superior cache to reduce the number of LLC write operations.Experimental results show that the proposed policy can reduce the average running time of all SPLASH-2 programs in a 4-core processor by 6.6%and the average cache energy consumption by 22.5%compared with the cache design without bypass policy.The policy effectively improves the overall cache performance.
Keywords:Non-Volatile Memory(NVM)  multicore processor  cache  reuse information  bypass policy  energy consumption
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