微米级平行互连线的测试结构设计

研究分析无串扰传输理想模型的条件,根据高速高密度电路板中微米级、亚毫米级互连线电磁串扰特性研究需要,首次提出微米级平行互连线的测试结构设计。经射频电路理论分析推导了测试结构对系统串扰没有影响。构建了有、无测试结构的微米级平行互连线物理模型,仿真分析后,加工制作有测试结构的微米级平行互连线电路板。研究结果表明,当数字基带信号传输频率在0~3 GHz 范围时,无测试结构仿真电路模型、有测试结构仿真电路模型、有测试结构的实验电路板,三者串扰特性吻合;微米级平行互连线的测试结构设计合理,具有工程参考价值。

Test Structure Design for Micron Parallel Interconnection

Studying the conditions of ideal model for crosstalk-free transmission, and based on the requirement on studying the crosstalk problem of high-speed and high-density interconnection within micron and sub-millimeter size, the test structure for micron parallel interconnection is designed. By the RF circuit theoretical analysis, it deduces that the designed test structure has no effect on the crosstalk of the system. The paper builds the physical model of parallel structure interconnection with and without test structure, and then tests the design and fabrication of micron parallel structure interconnection. The research results show when the transmission frequency of digital baseband signal is within 0-3 GHz, the crosstalk characteristics of the simulation circuit models with and without test structure and the experimental circuit board with test structure fit well; the design of test structure of micron level parallel interconnection is reasonable, and has engineering reference value.