基于FPGA伪随机码发生器的实现

文章讨论了在FPGA上利用线性反馈移位寄存器实现伪随机码发生器的方法，运用VHDL语言描述各部分的设计，这样不但利于随时修改而且还节省了设计的周期和简化了整个设计。此设计以Altera公司的QuartusⅡ为开发平台，经逻辑综合、布局布线后，适配到FPGA芯片中，给出了仿真结果，最后还给出了在示波器上显示的波形及其相关的分析。

The Implementation of Pseudo Random Number Generators Based on FPGA

This article discusses the method of using linear feedback shift registers to implement random number generators and use VHDL language to describe the design of each part. By doing so,not only can the design be modified anytime,but also can the period of design be reduced and the entire design be simplified. The design is based on Aletra's Quartus Ⅱ software and be fitted to FPGA chip after logic synthesizing and placement routing. The timing simulation result in placement and routing and interrelated analysis are also presented. The wave form which is displayed on the oscillograph is also presented at the end of this article.