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Cost-effective smart power CMOS/DMOS technology: design methodology for latch-up immunity |
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| Authors: | Bafleur M Vidal M Puig Buxo J Givelin Ph Macary V Sarrabayrouse G |
| Affiliation: | (1) Laboratoire et d'Analyse et d'Architecture des Systèmes du C.N.R.S., 7, Avenue du Colonel Roche, 31O77 Toulouse Cedex, France;(2) LCMM, Universitat de Barcelona, Diagonal 645-647, 08028 Barcelona, Spain;(3) Laboratoire et d'Analyse et d'Architecture des Systèmes du C.N.R.S., 7, Avenue du Colonel Roche, 31077 Toulouse Cedex, France;(4) Motorola Semiconducteurs, Avenue du Général Eisenhower, Le Mirail BP 1029, 31023 Toulouse Cedex, France;(5) Laboratoire et d'Analyse et d'Architecture des Systèmes du C.N.R.S., 7, Avenue du Colonel Roche, 31077 Toulouse Cedex, France |
| Abstract: | To answer to the need of a cost effective smart power technology, an original design methodology that permits implementing latch-up free smart power circuits on a very simple CMOS/DMOS technology is proposed. The basic concept used to this purpose is letting float the wells of the MOS transistors most susceptible to initiate latch-up. The efficiency of the design methodology is experimentally shown. |
| Keywords: | latch-up smart power CMOS technology design methodology |
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