| Adaboost算法并行硬件架构研究与FPGA验证 |
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| 引用本文： | 居然,赵峰.Adaboost算法并行硬件架构研究与FPGA验证[J].电子测量技术,2009(1):59-62. |
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| 作者姓名： | 居然 赵峰 |
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| 作者单位： | 上海交通大学微电子学院,上海,200240 |
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| 摘 要： | Adaboost算法级联目标检测方案使人脸检测向高速实时化迈进了一大步。但是该算法的计算复杂度高，需要存取的数据量非常大，如果采用纯软件的实现方案，会耗费相当多的CPU以及内存资源，难以达到实时检测的要求。本文分析了现有的Adaboost算法硬件架构，对访存效率，耗费的逻辑资源，检测速度等进行了分析，提出了一种基于检测窗口的阵列结构，利用硬件流水特性大大加速了检测过程。本设计通过Xilinx的Spartan3A-DSP型FPGA验证，可满足高清实时人脸检测的要求。
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| 关 键 词： | Adaboost 人脸检测 流水线 FPGA |
Parallel architecture design and FPGA verification of hardware adaboost algorithm |
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| Ju Ran,Zhao Feng.Parallel architecture design and FPGA verification of hardware adaboost algorithm[J].Electronic Measurement Technology,2009(1):59-62. |
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| Authors: | Ju Ran Zhao Feng |
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| Affiliation: | Shanghai Jiaotong University School of Microelectronics;Shanghai 200240 |
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| Abstract: | Adaboost algorithm makes it possible to implement real-time face detection system,but the soft algorithm can not work on embedded platform for real-time face detection due to its high computation load and data throughput.This article analyzes the memory efficiency and logic resource of hardware architecture,designs a new cell array architecture using parallel technology.Detection procedure can be greatly speeded up with its multi-pipelines.This design is verified on Xilinx Spartan3A-DSP FPGA.It can work wit... |
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| Keywords: | Adaboost FPGA |
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