| 有功电能计量IP核的设计 |
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| 引用本文： | 王艳,袁慧梅.有功电能计量IP核的设计[J].电子技术应用,2009,35(4). |
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| 作者姓名： | 王艳 袁慧梅 |
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| 作者单位： | 首都师范大学,信息工程学院,北京,100048 |
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| 摘 要： | 对有功电能计量的数学模型进行了分析,给出了相应的IP核实现模型,并详细讨论了CIC抽取滤波器、IIR高通滤波器、FIR低通滤波器、数字频率变换等模块的原理与设计。利用Simulink模型进行了仿真,用VHDL作为设计语言,在QuartusⅡ软件下完成综合和仿真,并在Altera公司的FPGA芯片CycloneⅡEP2C35F484C8目标板上实现设计。
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| 关 键 词： | 有功功率 FPGA CIC抽取滤波器 DFC |
The IP core design of active power metering |
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| WANG Yan,YUAN Hui Mei.The IP core design of active power metering[J].Application of Electronic Technique,2009,35(4). |
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| Authors: | WANG Yan YUAN Hui Mei |
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| Abstract: | This paper introduces the mathematic module of the active energy metering , and presents the corresponding IP core implementation model .The theory and design of cascade integrator comb(CIC) decimation filter, infinite impulse response(IIR) high pass filter, finite impulse response(FIR) low pass filter and digital frequency change(DFC) are introduced in detail.This design is simulated by Simulink, and designed with VHDL.Synthesis and simulation are completed by QuartusⅡ development tools.Finally, it has been implemented in Altera′s FPGA chip CycloneⅡ EP2C35F484C8. |
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| Keywords: | FPGA DFC |
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