首页 | 官方网站   微博 | 高级检索  
     

基于FPGA的数字幅频均衡器设计
引用本文:丁昊,宋杰,王国庆,关键.基于FPGA的数字幅频均衡器设计[J].电子测量技术,2010,33(10):48-51.
作者姓名:丁昊  宋杰  王国庆  关键
作者单位:海军航空工程学院信息融合技术研究所;
基金项目:国家自然科学基金资助项目,全国优秀博士学位论文作者专项基金资助项目
摘    要:研制了以FPGA为核心的数字幅频均衡器,在较宽的频带内校正了因传输系统不理想引起的信号幅度及相位失真。系统使用带阻滤波网络模拟信号的传输系统,利用Filter Solutions软件合理设定网络中元器件的参数,并得出其幅频特性。依据该特性,推导出与之匹配的均衡器参数,结合MATLAB软件的仿真分析结果,在FPGA中调用实现FIR滤波算法的IP核,对失真信号进行均衡处理。该均衡器具有实时性强、采样率高、动态范围大、稳定性高、通用性好等优点,可以实现对传输系统的理想均衡。

关 键 词:数字幅频均衡  FPGA  FIR滤波器  IP核

Design of digital equalizer based on FPGA devices
Ding Hao,Song Jie,Wang Guoqing,Guan Jian.Design of digital equalizer based on FPGA devices[J].Electronic Measurement Technology,2010,33(10):48-51.
Authors:Ding Hao  Song Jie  Wang Guoqing  Guan Jian
Affiliation:Ding Hao Song Jie Wang Guoqing Guan Jian(Research Institute of Information Fusion,Naval Aeronautical and Astronautical University,Yantai 264001)
Abstract:A new kind of digital equalizer is designed in this paper,which works with FPGA as core device.This system revises the signal's amplitude and phase distortion caused by the no ideal of the transmission system in a wide bandwidth.A band-stop filter network is adopted in the system to simulate signal's transmission system.Choosing reasonable parameters for each component in the network with the application of software called Filter Solutions,and then work out its amplitude-frequency characteristic.Figure out ...
Keywords:digital equalizer  FPGA  FIR filter  IP core  
本文献已被 CNKI 维普 万方数据 等数据库收录!
设为首页 | 免责声明 | 关于勤云 | 加入收藏

Copyright©北京勤云科技发展有限公司    京ICP备09084417号-23

京公网安备 11010802026262号