| 高帧频CCD驱动电路设计 |
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| 引用本文： | 李哲.高帧频CCD驱动电路设计[J].数字社区&智能家居,2014(12):8310-8312. |
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| 作者姓名： | 李哲 |
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| 作者单位： | 中国科学院长春光学精密机械与物理研究所,吉林长春130033 |
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| 摘 要： | 为了实现由Kodak KAI0340D CCD（Charge Coupled Device）组成的新型图像采集系统,需要设计专门的CCD时序驱动电路。使用Xilinx Spartan3AN FPGA（Field Programmable Gate Arrays）设计时序产生电路,经过驱动芯片MAX4426和ISL55110驱动,再经过箝位电路箝位,得到了满足CCD要求幅度和时序的驱动信号。经实验验证该方法产生了满足CCD要求的驱动时序,实际测试时CCD帧频达到了205.6frame/s。
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| 关 键 词： | 高帧频 面阵CCD FPGA 箝位电路 驱动电路 |
Design of High Frame Frequence CCD Driver Circuit |
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| LI Zhe.Design of High Frame Frequence CCD Driver Circuit[J].Digital Community & Smart Home,2014(12):8310-8312. |
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| Authors: | LI Zhe |
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| Affiliation: | LI Zhe (Changchun Institute of Optics, Fine Mechanics and Physics, Chinese Academy of Sciences, Changchun 130033, China) |
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| Abstract: | A special interline transfer aera-CCD（Charge Coupled Devic）driving circuit was designed for new pattern imaging system, using Kodak KAI0340D CCD as sensor. Xilinx Spartan3AN FPGA（ Field Programmable Gate Arrays） was used to generate timing driver signals. Then the signals were driven by MAX4426 and ISL55110, CMOS driver. Final, driven signals were clamped to certain voltage. By this way, needed CCD drive signals were achieved. Experimental result show that the CCD driver system is work well-balanced, and that the speed of CCD output is 205.6 frame/s. |
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| Keywords: | Aera-CCD High frame frequence FPGA Clamping circuit driving circuit |
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