| 基于CPLD多功能数字钟的优化设计 |
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| 引用本文： | 阮伟华.基于CPLD多功能数字钟的优化设计[J].南京工业职业技术学院学报,2010,10(2):36-38. |
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| 作者姓名： | 阮伟华 |
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| 作者单位： | 南京工业职业技术学院电气与电子工程学院,江苏南京210046 |
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| 摘 要： | 针对CPLD设计优化的问题,研究了如何在系统级及模块级对电路进行优化。通过系统级采用精简输入输出电路结构和模块级采用资源共享,逻辑优化等方法在CPLD芯片EPM7128SLC84-15上实现一个带有清零和校时的数字钟。综合之后,使用了112个LC,占总资源的87%,硬件电路运行稳定准确。
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| 关 键 词： | CPLD EPM7128 数字钟 优化 LC |
Optimization Design of Multiple Functional Digital Clock Based on CPLD |
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| RUAN Wei-hua.Optimization Design of Multiple Functional Digital Clock Based on CPLD[J].Journal of Nanjing Institute of Industry Technology,2010,10(2):36-38. |
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| Authors: | RUAN Wei-hua |
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| Affiliation: | RUAN Wei-hua(Nanjing Institute of Industry Technology,Nanjing 210046,China) |
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| Abstract: | This paper introduces the optimization design of CPLD,especially in the system level and the module level.A multiplier function digital clock based on the chip EPM7128SLC84-15 is realized by simplifying the architecture of inputs and outputs circuits in system level as well as optimizing the modules in module level.After synthesis,it is avail of 112 LCs,occupies 87% of the whole source.The hardware circuit runs steady and accurately. |
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| Keywords: | CPLD EPM7128 Digital Clock Optimization LC |
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