| 基于FPGA的TIADC并行采样系统设计 |
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| 引用本文： | 简磊,陈莹莹. 基于FPGA的TIADC并行采样系统设计[J]. 电子测试, 2017, 0(2). DOI: 10.3969/j.issn.1000-8519.2017.02.003 |
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| 作者姓名： | 简磊 陈莹莹 |
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| 作者单位： | 四川大学锦江学院,四川眉山,620860 |
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| 基金项目： | 四川大学锦江学院校级科研基金项目;项目 |
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| 摘 要： | 介绍一种基于多片ADC的时间交替并行采样设计方法以及在FPGA平台上的实现.着重阐述TIADC并行采样的增益误差、时间误差校正算法及实现.实验结果表明,TIADC并行数据采集系统的结构设计和预处理算法,能较好抑制因相位偏移、时钟抖动等造成的非均匀误差.
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| 关 键 词： | TIADC并行采样技术 时间非均匀误差 Farrow结构 AD9224 FPGA |
Design and Implementation of Parallel Acquisition System Based on TIADC and FPGA |
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| Jian Lei,Chen Yingying. Design and Implementation of Parallel Acquisition System Based on TIADC and FPGA[J]. Electronic Test, 2017, 0(2). DOI: 10.3969/j.issn.1000-8519.2017.02.003 |
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| Authors: | Jian Lei Chen Yingying |
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| Abstract: | The design method of a acquisition system based on multi-chip ADC times-interleaved parallel sampling technology and its realization on FPGA platform are introduced. The time non-uniform error and gain non-uniform error correction algorithm of time-interleaved parallel sampling system, and the realization of correction algorithm in hardware are emphasized. Test results indicate that the structural design of the time-interleaved parallel sampling system and the error correction algorithm can suppress the non-uniform error, which is caused by phase deviation and clock dithering. |
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| Keywords: | TIADC parallel sampling techniques time non-uniform error farrow structure AD9224 FPGA |
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