A quad 0.6-3.2 Gb/s/channel interference-free CMOS transceiver for backplane serial link |
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Authors: | Yongsam Moon Young-Soo Park Namhoon Kim Gijung Ahn Shin H.J. Deog-Kyoon Jeong |
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Affiliation: | Silicon Image Inc., Sunnyvale, CA, USA; |
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Abstract: | A quad-channel 0.6-3.2 Gb/s/channnel transceiver using eight independent phase-locked loops (PLLs) shows a 1-ps rms random jitter performance without interchannel interference. The PLL employs a folded starved inverter with high supply/substrate noise immunity and an analog coarse-tuning scheme for both seamless frequency acquisition and N-fold voltage-controlled-oscillator (VCO) gain reduction. A fixed-interval charge pumping is adopted for wide pumping-current range and large jitter tolerance. A wide-range delayed-locked loop (DLL) is utilized as a clock and reset generator for an elastic buffer. The transceiver, implemented in a 0.18-/spl mu/m CMOS technology, operates across a 30-in FR-4 backplane up to 3.2 Gb/s/ch with a bit-error rate of less than 10/sup -13/. |
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