| 一种应用于高速数据通信的LVDS接收器设计 |
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| 引用本文： | 孙金中,谢凤英.一种应用于高速数据通信的LVDS接收器设计[J].中国集成电路,2012(6):39-43. |
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| 作者姓名： | 孙金中 谢凤英 |
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| 作者单位： | 中国电子科技集团公司第38研究所,安徽合肥,230031 |
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| 摘 要： | 提出了一种应用于高速数据通讯的低电压差分信号(LVDS)接收器电路设计,符合IEEEStd.1596.3-1996(LVDS)标准,有效地解决了传统电路在低电源电压下不能满足标准对宽共模范围的要求以及系统的高速低功耗要求。电路采用65nm 1P9M CMOS Logic工艺设计实现,仿真结果表明该接收器电路能在符合标准的0V-2.4V的宽输入共模电平下稳定工作,在电源电压为2.5V的工作条件下,数据传输速率可以达到2Gbps,平均功耗仅为3mW。
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| 关 键 词： | 低压差分信号(LVDS) 接收器 差分信号 高速 |
Design of A LVDS Receiver for High Speed Data Communication IC |
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| SUN Jin-zhong,XIE Feng-ying.Design of A LVDS Receiver for High Speed Data Communication IC[J].China Integrated Circuit,2012(6):39-43. |
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| Authors: | SUN Jin-zhong XIE Feng-ying |
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| Affiliation: | (China Electronic Technology Group Corporation No.38 Research Institute,Hefei 230031 China) |
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| Abstract: | A high speed low power LVDS receiver was presented,which was fully compatible with IEEE Std 1596.3-1996 and used in high speed data communication IC.The receiver effectively overcome the problem of supports wide input common mode range from 0V to 2.4V in low power operation as specified by the standard.Based on 65nm 1P9M CMOS logic process,the simulation results show that the receiver has achieved a transmission rate up to 2 Gbps,with an average power consumption of 3 mW. |
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| Keywords: | Low-voltage differential signaling(LVDS) Receiver Differential signal High speed |
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