Hierarchical Delay Test Generation |
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Authors: | CP Ravikumar Nitin Agrawal Parul Agarwal |
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Affiliation: | (1) Department of Electrical Engineering, Indian Institute of Technology, New Delhi, 110016, INDIA;(2) S3 India, 5th Floor, Prestige Meredian, M.G. Road, Bangalore, 560001, INDIA;(3) Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, Michigan 48109, USA |
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Abstract: | Delay testing is used to detect timing errors in a digital circuit.In this paper, we report a tool called MODET forautomatic test generation for path delay faults in modular combinational circuits. Our technique usesprecomputed robust delay tests for individual modules to computerobust delay tests for the module-level circuit. We present alongest path theorem at the module level ofabstraction which specifies the requirements for path selectionduring delay testing. Based on this theorem, we propose a pathselection procedure in module-level circuits and report efficientalgorithms for delay test generation. MODET hasbeen tested against a number of hierarchical circuits with impressivespeedups in relation to gate-level test generation. |
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Keywords: | delay test generation hierarchical testing path selection |
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