AES算法的可配置硬件结构设计与实现

在分析AES算法的基础上,介绍了该算法各模块的设计实现方法,并将加解密运算结构设计为1个统一的结构。通过对密钥生成算法的分析,将3种密钥长度的密钥生成算法进行了可配置设计,使该设计能够实现加解密功能。该设计通过了FPGA仿真验证,与传统设计方案相比大大减小了硬件资源的消耗。

Design and implementation of configurable hardware architecture for AES

On the foundation of analyzing the AES algorithm, the method of implementation for each module of the algorithm is introduced, and a novel unified architecture for encryption and decryption is presented. After analysis of the key-generation algorithm, a configurable design for the three key-generation algorithms of different key length is given. So this design can fulfill the encryption/decryption function of different key length. After simulation and validation on FPGA, comparison with other traditional designs shows that this design can reduce the area cost greatly.