FFT算法的一种FPGA实现

FFT运算在OFDM系统中起调制和解调的作用。针对OFDM系统中FFT运算的要求，研究了一种易于FPGA实现的FFT处理器的硬件结构。接收单元采用乒乓RAM结构，扩大了数据吞吐量。中间数据缓存单元采用双口RAM，减少了访问RAM的时钟消耗。计算单元采用基2算法，流水线结构，可在4个时钟后连续输出运算结果。各个单元协调一致的并行工作，提高了系统时钟频率，达到了高速处理。采用块浮点机制，动态扩大数据范围，在速度和精度之间得到折衷。模块化设计，易于实现更多点数的FFT运算。

An Implementation of FFT Algorithm Based on FPGA

In OFDM system, the modulation and demodulation are realized by FFT to meet the demand of FFT in an OFDM system, a method of realizing FFT based on FPGA is introduced in this paper. The receiver block applies the structure of pingpang RAM which doubles the system throughput. The butterflyunit of radix2 is accelerated by pipeline architecture and the results can be achieved sequentially after three clocks delay. All of the components are synchronously and the high speed is gained. By using blockfloat, the dynamic range of data is adaptively increased and the advantage of speed and precision is compromised. Each component is designed separately. Hence the design is flexible to be extended to realize FFT of more points.