Junctionless Gate-all-around Nanowire FET with Asymmetric Spacer for Continued Scaling |
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| Authors: | Sreenivasulu V. Bharath Narendar Vadthiya |
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| Affiliation: | 1.Department of Electronics & Communication Engineering, National Institute of Technology Warangal, Warangal, Telangana, -506004, India
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| Abstract: | Silicon - In this paper, we have performed the scaling of asymmetric junctionless (JL) SOI nanowire (NW) FET at 10 nm gate length (LG). To study the device electrical performance various... |
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