| 采用vMOS管的多值计数器设计 |
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| 引用本文： | 汪鹏君,张跃军.采用vMOS管的多值计数器设计[J].电路与系统学报,2010,15(1). |
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| 作者姓名： | 汪鹏君 张跃军 |
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| 作者单位： | 宁波大学,电路与系统研究所,浙江,宁波,315211 |
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| 基金项目： | 国家自然科学基金(60776022);;浙江省科技计划项目(2008C21166);;浙江省教育厅重点科研项目(20061666);;宁波大学博士、教授基金 |
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| 摘 要： | 通过对νMOS管特性和多值逻辑电路设计原理的研究,本文提出一种新型多值计数器的设计方案。该方案利用νMOS管具有多输入栅加权信号控制及浮栅上的电容耦合效应等特性,结合二值逻辑编码方法,实现电路的多值输出。用PSPICE对所设计的电路模拟验证,结果表明,所设计的电路逻辑功能正确,结构简单,功耗低,且通用性强,易于实现。
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| 关 键 词： | νMOS管 多值逻辑 多值计数器 |
Design of multi-valued counter based on vMOS |
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| WANG Peng-jun,ZHANG Yue-jun.Design of multi-valued counter based on vMOS[J].Journal of Circuits and Systems,2010,15(1). |
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| Authors: | WANG Peng-jun ZHANG Yue-jun |
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| Affiliation: | Institute of Circuits and Systems;Ningbo University;Ningbo 315211;China |
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| Abstract: | Through the research on the characteristics of vMOS and the principles of multi-valued logic circuits, this paper presents a design scheme of multi-valued counter. Two-valued coding method and vMOS characteristics, including multiple-input signals threshold operation and the floating gate capacitance coupling effect, are integrated together to implement this proposed scheme. PSPICE simulation is selected to verify the proposed circuit. The simulation results indicate that this multi-valued counter can provide correct logic function, and has characters including simple structure, low power and easy in realization. |
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| Keywords: | vMOS multi-valued logic multi-valued counter |
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