| 片级三维寄生电容的并行提取算法 |
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| 引用本文： | 郑蓝舟,喻文健,尹航,王泽毅.片级三维寄生电容的并行提取算法[J].计算机辅助设计与图形学学报,2008,20(11). |
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| 作者姓名： | 郑蓝舟 喻文健 尹航 王泽毅 |
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| 作者单位： | 1. 清华大学计算机科学与技术系,北京,100084
2. 百度公司,北京,100080 |
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| 基金项目： | 国家自然科学基金，清华信息科学与技术国家实验室基础研究基金 |
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| 摘 要： | 随着多核CPU和分布式机群的日益普及,并行计算被日益广泛地应用于科学与工程实践中,以解决复杂的数值模拟问题.提出片级三维寄生电容的并行提取算法,它基于三维层次式块边界元素法,应用双向重叠组合思想将芯片划分为4类大小不同的"窗口";采用可变长的动态混合队列进行静态/动态结合的任务调度方法将全部"窗口"分配到不同进程,并在稀疏矩阵求和及进程间的规约求和运算中采用了提高并行效率的技术,达到了较好的负载平衡和较高的加速比.在分布式机群上采用消息传递接口编程的实验,验证了文中算法的有效性.
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| 关 键 词： | 并行计算 重叠组合法 三维寄生电容 全芯片提取 消息传递接口 |
A Parallel Algorithm for Chip-Level 3D Parasitic Capacitance Extraction |
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| Zheng Lanzhou,Yu Wenjian,Yin Hang,Wang Zeyi.A Parallel Algorithm for Chip-Level 3D Parasitic Capacitance Extraction[J].Journal of Computer-Aided Design & Computer Graphics,2008,20(11). |
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| Authors: | Zheng Lanzhou Yu Wenjian Yin Hang Wang Zeyi |
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| Affiliation: | Zheng Lanzhou~(1)) Yu Wenjian~(1)) Yin Hang~(2)) Wang Zeyi~(1)) ~(1))(Department of Computer Science , Technology,Tsinghua University,Beijing 100084) ~(2))(Baidu Company,Beijing 100080) |
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| Abstract: | With prevalence of multi-core CPU and distributed clusters,parallel computation is widely applied to scientific research as well as engineering practices,for solving complex numerical simulation problem.A parallel computational approach to the capacitance extraction is proposed, which is based on 3D hierarchical block boundary element method (HBBEM).It applies the two-way overlap and combination idea by dividing the chip into four kinds of thewindowswith different sizes, and then uses the variable-length mi... |
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| Keywords: | parallel computation overlap-combination method 3D parasitic capacitance full chip extraction message passing interface |
| 本文献已被 CNKI 维普 万方数据 等数据库收录！ |
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