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A framework for post-silicon realization of arbitrary instruction extensions on reconfigurable data-paths |
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| Affiliation: | 1. CAD Laboratory, Indian Institute of Science, Bangalore, India;2. Morphing Machines Pvt. Ltd, Bangalore 560055, India;3. T.U. Delft, Delft, Netherlands;1. Department of Nephrology, The Affiliated Hospital of Qingdao University, Qingdao 266003, Shandong, China;2. National Institute of Occupational Health and Poison Control, Chinese Center for Disease Control and Prevention, Beijing 100050, China;3. Department of Nephrology, The Second Hospital of Shandong University, Jinan 250100, Shandong, China;1. School of Computing and Mathematics, Keele University, Keele, Staffordshire ST5 5BG, UK;2. Università degli Studi di Modena e Reggio Emilia, Dipartimento di Ingegneria Enzo Ferrari, via Vivarelli 10, 41125 Modena, Italy;1. Department of Clinical Epidemiology, and Center of Evidence Based Medicine, The First Affiliated Hospital, China Medical University, Shenyang, China;2. School of Public Health, China Medical University, Shenyang, Liaoning, China;3. Department of Medical Center, The First Affiliated Hospital, China Medical University, Shenyang, China |
| Abstract: | In this paper we present a framework for realizing arbitrary instruction set extensions (IE) that are identified post-silicon. The proposed framework has two components viz., an IE synthesis methodology and the architecture of a reconfigurable data-path for realization of the such IEs. The IE synthesis methodology ensures maximal utilization of resources on the reconfigurable data-path. In this context we present the techniques used to realize IEs for applications that demand high throughput or those that must process data streams. The reconfigurable hardware called HyperCell comprises a reconfigurable execution fabric. The fabric is a collection of interconnected compute units. A typical use case of HyperCell is where it acts as a co-processor with a host and accelerates execution of IEs that are defined post-silicon. We demonstrate the effectiveness of our approach by evaluating the performance of some well-known integer kernels that are realized as IEs on HyperCell. Our methodology for realizing IEs through HyperCells permits overlapping of potentially all memory transactions with computations. We show significant improvement in performance for streaming applications over general purpose processor based solutions, by fully pipelining the data-path. |
| Keywords: | Reconfigurable computing Instruction extension Architecture exploration Hardware data-path Application acceleration |
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